Abstract: Embodiments of the present invention provide a method that comprises, within a sample window, determining an active time of a central processing unit (CPU) at an operating frequency. If there are any different operating frequencies within the sample window, the method further comprises determining active times of the CPU at the different operating frequencies within the sample window and, based upon the active times for the operating frequencies within the sample window, calculating a millions of instructions per second (MIPS) value for the sample window. The method further comprises performing a comparison of the MIPS value to a threshold value and, based upon the comparison of the MIPS value to the threshold value, setting an operating frequency of the CPU for a next sample window.

Abstract: Systems, methods, and other embodiments associated with a low power audio codec are described. According to one embodiment, an audio codec includes an audio buffer configured to store decoded audio data received from an application processor external to the audio codec. The application processor is configured to decode audio data in a RUN mode. The audio codec is configured to store, in the audio buffer, decoded audio data received from the application processor when the application processor is in IDLE mode and provide the stored decoded audio data to an audio device while the application processor is in a low power mode.

Abstract: Systems and methods are provided for noise reduction. An input audio signal is received. A target gain corresponding to a target volume level is determined. One or more increments of gain change are determined to reach the target gain. A first non-zero amplitude in the input audio signal is detected. The first non-zero amplitude is not within a predetermined range of zero amplitude. Upon the detection of the first non-zero amplitude in the input audio signal, the one or more increments of gain change are applied at one or more zero-crossing points of the input audio signal. The input audio signal is within the predetermined range of zero amplitude at the one or more zero-crossing points. An output audio signal is generated.

Abstract: Systems, methods, and other embodiments associated with a low power audio codec are described. According to one embodiment, an apparatus includes an audio codec having an audio buffer configured to store decoded audio data received from a processor. The audio codec is configured to provide the stored decoded audio data to an audio device while decoded audio data is not being received from the processor. According to another embodiment, a method includes receiving a request for decoded audio data from an audio codec with an audio buffer, entering a RUN mode and providing decoded audio data stored in processor memory to the audio codec for storage in the audio buffer. After receiving a buffer full signal from the audio codec the method includes entering a low power mode while the audio codec provides an audio signal to an audio device.

Abstract: Embodiments of the present invention provide a method that comprises, within a sample window, determining an active time of a central processing unit (CPU) at an operating frequency. If there are any different operating frequencies within the sample window, the method further comprises determining active times of the CPU at the different operating frequencies within the sample window and, based upon the active times for the operating frequencies within the sample window, calculating a millions of instructions per second (MIPS) value for the sample window. The method further comprises performing a comparison of the MIPS value to a threshold value and, based upon the comparison of the MIPS value to the threshold value, setting an operating frequency of the CPU for a next sample window.

Abstract: Embodiments of techniques for simultaneously connecting a plurality of expansion cards to a single bus of a host controller are described.

Abstract: Embodiments of techniques for simultaneously connecting a plurality of expansion cards to a single bus of a host controller are described.