Patents by Inventor Qiuling Zhu
Qiuling Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170310855Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.Type: ApplicationFiled: May 9, 2017Publication date: October 26, 2017Applicant: Google Inc.Inventors: Ofer Shacham, Jason Rupert Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson, Donald Stark
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Publication number: 20170287105Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Inventors: Albert Meixner, Hyunchul Park, Qiuling Zhu, Jason Rupert Redgrave
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Patent number: 9772852Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.Type: GrantFiled: April 23, 2015Date of Patent: September 26, 2017Assignee: Google Inc.Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
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Patent number: 9769356Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.Type: GrantFiled: April 23, 2015Date of Patent: September 19, 2017Assignee: Google Inc.Inventors: Ofer Shacham, Jason Rupert Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson, Donald Stark
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Publication number: 20170257585Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.Type: ApplicationFiled: May 17, 2017Publication date: September 7, 2017Applicant: Google Inc.Inventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
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Publication number: 20170257515Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Applicant: Google Inc.Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein
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Publication number: 20170256021Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Applicant: Google Inc.Inventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward Chang, William Mark
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Patent number: 9756268Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.Type: GrantFiled: April 23, 2015Date of Patent: September 5, 2017Assignee: Google Inc.Inventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
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Publication number: 20170249153Abstract: An apparatus is described. The apparatus includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Applicant: Google Inc.Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
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Publication number: 20170249717Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.Type: ApplicationFiled: February 8, 2017Publication date: August 31, 2017Inventors: Albert MEIXNER, Hyunchul PARK, Qiuling ZHU, Jason Rupert REDGRAVE
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Patent number: 9749548Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.Type: GrantFiled: January 22, 2015Date of Patent: August 29, 2017Assignee: Google Inc.Inventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner
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Publication number: 20170242943Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.Type: ApplicationFiled: May 10, 2017Publication date: August 24, 2017Applicant: Google Inc.Inventors: Albert Meixner, Ofer Shacham, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu, Jason Rupert Redgrave
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Publication number: 20170206627Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S-1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.Type: ApplicationFiled: April 4, 2017Publication date: July 20, 2017Applicant: Google Inc.Inventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner
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Publication number: 20160313999Abstract: An apparatus is described. The apparatus includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lanes of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.Type: ApplicationFiled: April 23, 2015Publication date: October 27, 2016Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
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Publication number: 20160316107Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.Type: ApplicationFiled: April 23, 2015Publication date: October 27, 2016Inventors: Ofer Shacham, Jason Rupert Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson, Donald Stark
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Publication number: 20160316157Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.Type: ApplicationFiled: April 23, 2015Publication date: October 27, 2016Inventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
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Publication number: 20160316094Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.Type: ApplicationFiled: April 23, 2015Publication date: October 27, 2016Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein
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Publication number: 20160313980Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.Type: ApplicationFiled: April 23, 2015Publication date: October 27, 2016Inventors: Albert Meixner, Ofer Shacham, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu, Jason Rupert Redgrave
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Publication number: 20160314555Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors.Type: ApplicationFiled: April 23, 2015Publication date: October 27, 2016Inventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward T. Chang, William R. Mark
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Publication number: 20160219225Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.Type: ApplicationFiled: January 22, 2015Publication date: July 28, 2016Inventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner