Patents by Inventor Qiuyi Ye
Qiuyi Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7561483Abstract: An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.Type: GrantFiled: March 14, 2007Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
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Patent number: 7558136Abstract: A memory cell having an asymmetric connection for evaluating dynamic stability provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By operating the cell and observing changes in performance caused by the asymmetry, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each crosscoupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.Type: GrantFiled: August 14, 2007Date of Patent: July 7, 2009Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
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Patent number: 7515491Abstract: A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.Type: GrantFiled: March 14, 2007Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
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Patent number: 7483322Abstract: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.Type: GrantFiled: December 22, 2007Date of Patent: January 27, 2009Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Qiuyi Ye, Yuen H. Chan, Anirudh Devgan
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Patent number: 7376001Abstract: A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator implemented in a row of memory cells and having outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells is operated by the method. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.Type: GrantFiled: October 13, 2005Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Qiuyi Ye, Yuen H. Chan, Anirudh Devgan
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Publication number: 20080094878Abstract: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.Type: ApplicationFiled: December 22, 2007Publication date: April 24, 2008Inventors: Rajiv Joshi, Qiuyi Ye, Yuen Chan, Anirudh Devgan
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Publication number: 20070291562Abstract: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.Type: ApplicationFiled: August 14, 2007Publication date: December 20, 2007Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
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Patent number: 7304895Abstract: Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.Type: GrantFiled: September 13, 2005Date of Patent: December 4, 2007Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
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Patent number: 7301835Abstract: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.Type: GrantFiled: September 13, 2005Date of Patent: November 27, 2007Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Qiuyi Ye, Anirudh Devgan
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Publication number: 20070165471Abstract: An internally asymmetric method for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.Type: ApplicationFiled: March 14, 2007Publication date: July 19, 2007Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
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Publication number: 20070153599Abstract: A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.Type: ApplicationFiled: March 14, 2007Publication date: July 5, 2007Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
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Publication number: 20070086232Abstract: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.Type: ApplicationFiled: October 13, 2005Publication date: April 19, 2007Inventors: Rajiv Joshi, Qiuyi Ye, Yuen Chan, Anirudh Devgan
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Publication number: 20070058448Abstract: Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.Type: ApplicationFiled: September 13, 2005Publication date: March 15, 2007Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
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Publication number: 20070058466Abstract: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.Type: ApplicationFiled: September 13, 2005Publication date: March 15, 2007Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
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Patent number: 7015552Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: GrantFiled: April 4, 2005Date of Patent: March 21, 2006Assignee: International Business Machines CorporationInventors: Qiuyi Ye, William R. Tonti, Yujun Li
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Publication number: 20050199966Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: ApplicationFiled: April 4, 2005Publication date: September 15, 2005Applicant: International Business Machines CorporationInventors: Qiuyi Ye, William Tonti, Yujun Li
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Patent number: 6908815Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: GrantFiled: July 22, 2003Date of Patent: June 21, 2005Assignee: International Business Machines CorporationInventors: Qiuyi Ye, William R. Tonti, Yujun Li
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Publication number: 20040108555Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: ApplicationFiled: July 22, 2003Publication date: June 10, 2004Applicant: International Business Machines CorporationInventors: Qiuyi Ye, William R. Tonti, Yujun Li
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Patent number: 6642584Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: GrantFiled: January 30, 2001Date of Patent: November 4, 2003Assignee: International Business Machines CorporationInventors: Qiuyi Ye, William R. Tonti, Yujun Li
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Patent number: 6528855Abstract: A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.Type: GrantFiled: July 24, 2001Date of Patent: March 4, 2003Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Qiuyi Ye, William Tonti, Yujun Li, Jack A. Mandelman