Patents by Inventor Quanbo LI
Quanbo LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11849868Abstract: A connecting device for interconnecting a vertical tube and a plurality of display cabinets for carrying display modules includes first and second connecting frames and a fastening unit. The first connecting frame is for mounting the display cabinets thereon, abuts against a front outer surface of the vertical tube facing the display cabinets. The second connecting frame abuts against a rear outer surface of the vertical tube facing away from the first connecting frame. The fastening unit includes first fastening sets fastening the first and second connecting frames together so as to clamp the vertical tube therebetween. The second fastening sets fasten securely the display cabinets to the first connecting frame.Type: GrantFiled: April 19, 2021Date of Patent: December 26, 2023Assignee: Top Victory Investments LimitedInventors: Quanbo Li, Guoliang Wang, Li-Wei Lin, Kuo-Hua Liao
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Publication number: 20230130629Abstract: The present application relates to a method for making silicon epitaxy of a FDSOI device, which includes the following steps: providing a semiconductor structure; sequentially forming a first etch stop layer and an etch reaction layer on a surface of the semiconductor structure; performing an etching operation to the etch reaction layer to form a sidewall structure respectively; filling a second etch stop layer in a space between the sidewall structures at the position of the trench; etching the sidewall structures and the first etch stop layer under the sidewall structures to form a groove structure; removing the second etch stop layer and the remaining first etch stop layer; enabling a silicon substrate at the positions of the trench and the groove structure to epitaxially grow upwards to form epitaxial silicon, the epitaxial silicon being in flush with a top silicon layer.Type: ApplicationFiled: September 23, 2022Publication date: April 27, 2023Applicant: Shanghai Huali Integrated Circuit CorporationInventors: Lian Lu, Quanbo Li, Jun Huang
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Publication number: 20220133061Abstract: A connecting device for interconnecting a vertical tube and a plurality of display cabinets for carrying display modules includes first and second connecting frames and a fastening unit. The first connecting frame is for mounting the display cabinets thereon, abuts against a front outer surface of the vertical tube facing the display cabinets. The second connecting frame abuts against a rear outer surface of the vertical tube facing away from the first connecting frame. The fastening unit includes first fastening sets fastening the first and second connecting frames together so as to clamp the vertical tube therebetween. The second fastening sets fasten securely the display cabinets to the first connecting frame.Type: ApplicationFiled: April 19, 2021Publication date: May 5, 2022Applicant: Top Victory Investments LimitedInventors: Quanbo Li, Guoliang Wang, Li-Wei Lin, Kuo-Hua Liao
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Patent number: 9449866Abstract: The invention discloses a treatment process for a semiconductor, comprising providing a substrate, the substrate comprises silicon material; defining a trench region; removing the trench region using a plasma etching process and exposing a trench surface, the trench surface comprising surface defects; forming an oxidation layer overlaying the trench surface; removing the oxidation layer and at least a portion of the surface defects; expositing a treated trench surface, the treated trench surface being substantially free from surface defects; and forming a layer of silicon germanium material overlaying the treated trench surface. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance. In the treatment process, a substrate is subjected to at least one oxidation-deoxidation processes, where an oxidation layer is formed and then removed.Type: GrantFiled: January 6, 2015Date of Patent: September 20, 2016Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Quanbo Li, Jun Huang, Xiangguo Meng, Yu Zhang
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Publication number: 20160218005Abstract: A process is used to form a protective layer to cover a divot between two regions of a semiconductor material. During etching processes, the protective layer protects the divot to be etched away and reduces material loss of a Silicon (Si)-shallow trench isolation (STI) substrate. A selective coverage is provided to protect the height of the Si-STI substrate and an Si-STI interface. A desirable geometry can be obtained for forming a silicon germanium (SiGe)layer with uniform thickness near the divot.Type: ApplicationFiled: April 20, 2015Publication date: July 28, 2016Inventors: Quanbo Li, Jun Huang, Xiangguo Meng
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Patent number: 9390915Abstract: A process is used to form a protective layer to cover a divot between two regions of a semiconductor material. During etching processes, the protective layer protects the divot to be etched away and reduces material loss of a Silicon (Si)-shallow trench isolation (STI) substrate. A selective coverage is provided to protect the height of the Si-STI substrate and an Si-STI interface. A desirable geometry can be obtained for forming a silicon germanium (SiGe)layer with uniform thickness near the divot.Type: GrantFiled: April 20, 2015Date of Patent: July 12, 2016Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Quanbo Li, Jun Huang, Xiangguo Meng
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Patent number: 9171731Abstract: The invention relates to microelectronic technology and, more specifically, relates to a method of forming a gate with a LELE double pattern. The method adopts an ONO structure (Oxide-SiN-Oxide). The ONO structure is exposed twice, and the advanced patterning film is used as a mask in the processing of polysilicon etching. The ONO structure is used to replace the traditional hardmask of silicon oxide, and the substructure of ODL (Organic Under Layer) which is based on the spin-on, and the middle layer structure of SHB (Si-based hardmask). The method saves cost and improves the process of advanced patterning film as a mask with the nodes in 40 nm and above which is applied to the process with the nodes in 22/20 nm and below. Consequently, the maturity and stability of the process for poly gate with the nodes in 22/20 nm and below are improved.Type: GrantFiled: November 20, 2013Date of Patent: October 27, 2015Assignee: Shanghai Huali Microelectronics CorporationInventors: Jun Huang, ZhiBiao Mao, QuanBo Li, ZhiFeng Gan, RunLing Li
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Publication number: 20150270127Abstract: The invention discloses a treatment process for a semiconductor, comprising providing a substrate, the substrate comprises silicon material; defining a trench region; removing the trench region using a plasma etching process and exposing a trench surface, the trench surface comprising surface defects; forming an oxidation layer overlaying the trench surface; removing the oxidation layer and at least a portion of the surface defects; expositing a treated trench surface, the treated trench surface being substantially free from surface defects; and forming a layer of silicon germanium material overlaying the treated trench surface. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance. In the treatment process, a substrate is subjected to at least one oxidation-deoxidation processes, where an oxidation layer is formed and then removed.Type: ApplicationFiled: January 6, 2015Publication date: September 24, 2015Inventors: Quanbo Li, Jun Huang, Xiangguo Meng, Yu Zhang
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Publication number: 20150050801Abstract: The invention relates to microelectronic technology and, more specifically, relates to a method of forming a gate with a LELE double pattern. The method adopts an ONO structure (Oxide-SiN-Oxide). The ONO structure is exposed twice, and the advanced patterning film is used as a mask in the processing of polysilicon etching. The ONO structure is used to replace the traditional hardmask of silicon oxide, and the substructure of ODL (Organic Under Layer) which is based on the spin-on, and the middle layer structure of SHB (Si-based hardmask). The method saves cost and improves the process of advanced patterning film as a mask with the nodes in 40 nm and above which is applied to the process with the nodes in 22/20 nm and below. Consequently, the maturity and stability of the process for poly gate with the nodes in 22/20 nm and below are improved.Type: ApplicationFiled: November 20, 2013Publication date: February 19, 2015Applicant: Shanghai Huali Microelectronics CorporationInventors: Jun HUANG, ZhiBiao MAO, QuanBo LI, ZhiFeng GAN, RunLing LI
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Publication number: 20140357056Abstract: A method of forming a ?-shaped trench is disclosed. The method includes: providing a silicon substrate; and performing a plasma etching process to form a ?-shaped trench in the silicon substrate. The plasma etching process includes: etching the silicon substrate using a first plasma etching gas including a sulphur-containing fluoride; and etching the silicon substrate using a second plasma etching gas including a sulphur-containing fluoride and a polymer gas. A method of forming a semiconductor device is also disclosed.Type: ApplicationFiled: November 27, 2013Publication date: December 4, 2014Applicant: Shanghai Huali Microelectronics CorporationInventors: Quanbo Li, Yu Zhang, Jun Huang, Shu Koon Pang
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Publication number: 20140322879Abstract: A method of forming a ?-shaped trench is disclosed. The method includes: providing a silicon substrate; and sequentially performing a plasma etching process and a wet etching process on the silicon substrate to form a ?-shaped trench therein. The plasma etching process includes: horizontally etching the silicon substrate using a first plasma etching gas including a nitrogen-containing fluoride; and vertically etching the silicon substrate using a second plasma etching gas including a polymer gas. A method of forming a semiconductor device is also disclosed.Type: ApplicationFiled: November 21, 2013Publication date: October 30, 2014Applicant: Shanghai Huali Microelectronics CorproationInventors: Quanbo LI, Fang LI, Yu ZHANG, Jingxun FANG, Shu Koon PANG