Abstract: An aspect of the present invention provides a method of segmenting an input image into a plurality of segments. The method comprises the steps of: deriving an image representative of boundary strength of each of a plurality of pixels in the input image; adding a random noise pattern to at least a portion of the derived image; determining a plurality of local minima in the derived image with the random noise pattern added, each of the plurality of local minima comprising a point with a lowest measure of boundary strength within a pre-defined region in the derived image; and associating each of the plurality of pixels in the input image with one of the determined local minima to segment the image based on a geodesic distance transform of the measure between the determined local minima and the pixels.

Abstract: A method for determining a shift between two images, determining a first correlation in a first direction, the first correlation being derived from a first image projection characteristics and a second image projection characteristics, and a second correlation in a second direction, the second correlation being derived from the first image projection characteristics and the second image projection characteristics. The method determines a set of hypotheses from a first plurality of local maxima of the first correlation and a second plurality of local maxima of the second correlation. The method then calculates a two-dimensional correlation score between the first image and the second image based on a shift indicated in at least one of the set of hypotheses, and selecting one of the set of hypotheses as the shift between the first image and the second image based on the calculated two-dimensional correlation score.

Abstract: A method of managing place data for a mobile device, the method comprising storing place data for the mobile device in a centralized place data store, the centralized place data store storing location data for each of a plurality of places defined by the mobile device, and in response to place data requests from a plurality of applications executing on the mobile device, providing the place data from the centralized place data store to the plurality of applications.

Abstract: A method of managing place data for a mobile device, the method comprising storing place data for the mobile device in a centralized place data store, the centralized place data store storing location data for each of a plurality of places defined by the mobile device, and in response to place data requests from a plurality of applications executing on the mobile device, providing the place data from the centralized place data store to the plurality of applications.

Abstract: A method of determining a focus parameter for aligning a water in an exposure tool within a measurement tolerance required for the exposure tool, the exposure tool using a lens system for alignment. A test chart is provided having a sharp auto-correlation associated with the wafer. An image of the test chart is captured using a lens pupil mask having at least two phase ramps that are non-parallel. The captured image of the test charge is auto-correlated to determine the position of the test chart relative to a focal position of the lens system. The focus parameter for alignment of the wafer is determined using the determined position of the test chart, whereby the focus parameter is determined within the measurement tolerance required by the exposure tool.

Abstract: Methods for determining a depth measurement of a scene which involve capturing at least two images of the scene with different camera parameters, and selecting corresponding image patches in each scene. A first approach calculates a plurality of complex responses for each image patch using a plurality of different quadrature filters, each complex response having a magnitude and a phase, assigns, for each quadrature filter, a weighting to the complex responses in the corresponding image patches, the weighting being determined by a relationship of the phases of the complex responses, and determines the depth measurement of the scene from a combination of the weighted complex responses.

Abstract: A memory circuit includes a memory including a plurality of primary memory elements, and an error correction circuit coupled to the memory and operative to detect an error in at least one of the primary memory elements and to provide corrected data corresponding to the primary memory element. The memory circuit further includes at least one spare memory element and a control circuit operative to replace at least one of the primary memory elements with the spare memory element as a function of results generated by the error correction circuit.

Abstract: A technique determines a depth measurement associated with a scene captured by an image capture device. The technique receives at least first and second images of the scene, in which the first image is captured using at least one different camera parameter than that of the second image. At least first and second image patches are selected from the first and second images, respectively, the selected patches corresponding to a common part of the scene. The selected image patches are used to determine which of the selected image patches provides a more focused representation of the common part. At least one value is calculated based on a combination of data in the first and second image patches, the combination being dependent on the more focused image patch. The depth measurement of the common part of the scene is determined from the at least one calculated value.

Abstract: A method for determining a shift between two images, determining a first correlation in a first direction, the first correlation being derived from a first image projection characteristics and a second image projection characteristics, and a second correlation in a second direction, the second correlation being derived from the first image projection characteristics and the second image projection characteristics. The method determines a set of hypotheses from a first plurality of local maxima of the first correlation and a second plurality of local maxima of the second correlation. The method then calculates a two-dimensional correlation score between the first image and the second image based on a shift indicated in at least one of the set of hypotheses, and selecting one of the set of hypotheses as the shift between the first image and the second image based on the calculated two-dimensional correlation score.

Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.

Abstract: Disclosed herein is a method of estimating a geometrical relationship between a first image (101) and a second image (102), wherein the second image (102) includes a noise component. The method determines a location and size of each one of a plurality of image patches (201), based on the noise component included in the second image (102) and correlation information derived from the first image (101). The method then identifies a plurality of first image areas in the first image and a corresponding plurality of second image areas in the second image, based on the location and size of each one of the plurality of image patches. Each first image area of the first image (101) corresponds to a related second image area of the second image (102).

Abstract: A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors.

Abstract: A method (500) of determining rotation and scale transformation parameters is disclosed. The method (500) determines a plurality of weight values associated with one or more parts of at least one of a first and second image (e.g., 154. 155). A representation of each of the first and second images (154. 155) is formed using the weight values, the representation being substantially invariant to translation of the first and second images (154. 155). Rotation and scale transformation parameters relating the first and second images (154. 155) are determined based on the representation of each of the first and second images (154. 155). The rotation and scale transformation parameters are stored.

Abstract: A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors.

Abstract: A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.

Abstract: A method and system to compare rendered publication data. The publication data are accessed from a database and then rendered to produce rendered publication data. The rendered publication data are stored to provide a reference version. After a periodic time interval, the publication data are accessed again and rendered to product a second version of rendered publication data. The reference version and the second version of rendered publication data are compared and a notification is generated when a difference exists.

Abstract: A memory cell comprises a storage element including a transistor and an inverter. The inverter has an input coupled to a first source/drain of the transistor at a first node and has an output coupled to a gate of the transistor at a second node. The transistor has a second source/drain coupled to a voltage supply of the memory circuit. The memory cell further includes a switching element coupled to the storage element at the first node and being operative to selectively access the storage element as a function of a control signal supplied to a control input of the switching element. The storage element is operative to store at least first and second data states. The first data state is retained in the storage element by maintaining the first node at a first voltage level by leakage current and by maintaining the second node at a second voltage level by active current.

Abstract: A method and system to verify active content in a server system include receiving a communication (e.g., an e-mail message or an e-commerce listing) that includes active content to be made accessible by the server system. A reference (e.g., a URL) within the active content is identified, the reference pointing to further data that is not included within the communication. This further data is to be retrieved when the active content is rendered. The reference is stored at the server system, and the further data, to which the reference points, is repetitively and periodically retrieved. Subsequent to each retrieval of the further data, a determination is made as to whether the further data is malicious.

Abstract: Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.

Abstract: An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level.