Abstract: A system for generating an advanced surround view for a vehicle includes a plurality of cameras to generate image data. Sensors are configured to determine kinematic data of the vehicle. Kinematic data are also obtained by a visual odometry module and/or a deep-vision mechanism. A processor is configured to process image data captured by the plurality of cameras to generate a 360-degree surround view layer representative of a surrounding area. The processor is further configured to construct an improved bicycle kinematic model for processing kinematic data to generate an under-chassis layer representative of an area under the vehicle. The processor is further configured to generate a 3D vehicle model layer and overlay objects layer. Display screens display a GUI of combined scene of the 360-degree surround view layer, under-chassis layer, 3D vehicle model layer and overlay objects layer as would be viewed from a virtual camera viewpoint.

Abstract: A method of calibrating a pump system can include providing a pump, calibrating a pump input with an input device connected to the pump, and calibrating a pump output with an output device connected to the pump. Calibrating the pump input can include selecting a first input signal value, generating a transmitted input signal corresponding to the first input signal value, and setting a nominative pump input value to the first input signal value. Calibrating the pump output can include receiving a received output signal outputted from the pump, and setting a nominative pump output value to the first input signal value.

Abstract: Disclosed are articles having a thermoplastic photochromic coating. The articles exhibit a Bayer Abrasion ratio of at least 2 and desirable photochromic properties, i.e., the formation of darker activated colors and faster rates of photochromic activation and fade when irradiated with ultraviolet light.

Abstract: Disclosed are articles having a thermoplastic photochromic coating. The articles exhibit a Bayer Abrasion ratio of at least 2 and desirable photochromic properties, i.e., the formation of darker activated colors and faster rates of photochromic activation and fade when irradiated with ultraviolet light.

Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Abstract: A method of autonomously sharing a load between at least two output generation devices, the method including: providing at least two output generation devices, wherein the at least two output generation devices operate autonomously with respect to one another and the at least two output generation devices are in fluid communication with output receiving means adapted to receive output generated by the at least two output generation devices; monitoring output generated by the output generation devices; and cycling each of the at least two devices through an activated mode and a standby mode independently of one another in an automated manner to meet an output demand thereby sharing a load demand between the at least two output generation devices.

Abstract: A method of autonomously sharing a load between at least two output generation devices, the method including: providing at least two output generation devices, wherein the at least two output generation devices operate autonomously with respect to one another and the at least two output generation devices are in fluid communication with output receiving means adapted to receive output generated by the at least two output generation devices; monitoring output generated by the output generation devices; and cycling each of the at least two devices through an activated mode and a standby mode independently of one another in an automated manner to meet an output demand thereby sharing a load demand between the at least two output generation devices.

Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Abstract: An electroluminescent device, including a spaced-apart anode and cathode and an organic layer disposed between the spaced-apart anode and cathode and including a polymer having arylamine repeating unit moiety represented by formula wherein: Ar, Ar1, Ar2, Ar3, and Ar4 are each individually arylof from 6 to 60 carbon atoms; or a heteroarylof from 4 to 60 carbons, or combinations thereof; or Ar1 and Ar2, Ar3 and Ar4, Ar1 and Ar4, Ar2 and Ar4 are connected through a chemical bond; and X is a conjugated group having 2 to 60 carbon atoms.

Abstract: An electroluminescent device, including a spaced-apart anode and cathode and an organic layer disposed between the spaced-apart anode and cathode and including a polymer having arylamine repeating unit moiety represented by formula wherein: Ar, Ar1, Ar2, Ar3, and Ar4 are each individually arylof from 6 to 60 carbon atoms; or a heteroarylof from 4 to 60 carbons, or combinations thereof; or Ar1 and Ar2, Ar3 and Ar4, Ar1 and Ar4, Ar2 and Ar4 are connected through a chemical bond; and X is a conjugated group having 2 to 60 carbon atoms.

Abstract: In accordance with one aspect of the current invention, the system comprises a memory for storing instruction sequences by which the processor-based system is processed, where the memory includes a physical memory and a virtual memory. The system also comprises a processor for executing the stored instruction sequences. The stored instruction sequences include process acts to cause the processor to: map a plurality of predetermined instruction sequences from the physical memory to the virtual memory, determine an offset to one of the plurality of predetermined instruction sequences in the virtual memory, receive an instruction to execute the one of the plurality of predetermined instruction sequences, transfer control to the one of the plurality of predetermined instruction sequences, and process the one of the plurality of predetermined instruction sequences from the virtual memory.

Abstract: A method and apparatus for secure processing of cryptographic keys, wherein a cryptographic key stored on a token is processed in a secure processor mode using a secure memory. A main system processor is initialized into a secure processing mode, which cannot be interrupted by other interrupts, during a power-on sequence. A user enters a Personal Identification Number (PIN) to unlock the cryptographic key stored on the token. The cryptographic key and associated cryptographic program are then loaded into the secure memory. The secure memory is locked to prevent access to the stored data from any other processes. The user is then prompted to remove the token and the processor exits the secure mode and the system continues normal boot-up operations. When an application requests security processing, the cryptographic program is executed by the processor in the secure mode such that no other programs or processes can observe the execution of the program.

Abstract: A method and apparatus for secure processing of cryptographic keys, wherein a cryptographic key stored on a token is processed in a secure processor mode using a secure memory. A main system processor is initialized into a secure processing mode, which cannot be interrupted by other interrupts, during a power-on sequence. A user enters a Personal Identification Number (PIN) to unlock the cryptographic key stored on the token. The cryptographic key and associated cryptographic program are then loaded into the secure memory. The secure memory is locked to prevent access to the stored data from any other processes. The user is then prompted to remove the token and the processor exits the secure mode and the system continues normal boot-up operations. When an application requests security processing, the cryptographic program is executed by the processor in the secure mode such that no other programs or processes can observe the execution of the program.

Abstract: A method and apparatus for secure processing of cryptographic keys, wherein a cryptographic key stored on a token is processed in a secure processor mode using a secure memory. A main system processor is initialized into a secure processing mode, which cannot be interrupted by other interrupts, during a power-on sequence. A user enters a Personal Identification Number (PIN) to unlock the cryptographic key stored on the token. The cryptographic key and associated cryptographic program are then loaded into the secure memory. The secure memory is locked to prevent access to the stored data from any other processes. The user is then prompted to remove the token and the processor exits the secure mode and the system continues normal boot-up operations. When an application requests security processing, the cryptographic program is executed by the processor in the secure mode such that no other programs or processes can observe the execution of the program.

Abstract: A method for validating expansion ROM cards which are loaded into a Personal Computer. A ROM image is signed (encrypted) using a private key and an encryption algorithm to create a digital signature. The digital signature is stored along with the ROM image on an expansion ROM. The system BIOS scans the system for the presence of an expansion ROM and when one is detected, the digital signature is verified (decrypted) using a public key corresponding to the private key. If the decrypted digital signature matches the ROM image (or a hash digest thereof), then the BIOS loads the ROM image.

Abstract: In accordance with one aspect of the current invention, the system comprises a memory for storing instruction sequences by which the processor-based system is processed, where the memory includes a physical memory and a virtual memory. The system also comprises a processor for executing the stored instruction sequences. The stored instruction sequences include process acts to cause the processor to: map a plurality of predetermined instruction sequences from the physical memory to the virtual memory, determine an offset to one of the plurality of predetermined instruction sequences in the virtual memory, receive an instruction to execute the one of the plurality of predetermined instruction sequences, transfer control to the one of the plurality of predetermined instruction sequences, and process the one of the plurality of predetermined instruction sequences from the virtual memory.

Abstract: A method of designing an integrated circuit employs hardware testing rule checking so as to ensure hardware testability and to ensure that automated test program generation will succeed when the design cycle reaches that stage. The method calls for, first, receiving a proposed logic design defined at a functional or behavioral level; second, defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design for verifying the operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and, prior to releasing the logic design for logic synthesis, checking the simulation for compliance with the hardware testing rule set. Preliminary checking of the design and test bench prior to synthesis can avoid costly corrections later in connection with test program generation.