Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the

Abstract: The invention relates to a method for determining the phase difference between a first clock signal (CK1) received by a first electronic component (CE1) and a second clock signal (CK2) received by a second electronic component (CE2), comprising the steps of: S10) transmitting a first calibration signal (S12); S20) measuring a first delay (T1); S30) transmitting a second calibration signal (S21); S40) measuring a second delay (T2); S50) measuring the number (n) of clock pulses between the transmission of the first calibration signal (S12) and the active edge of the first clock signal (CK1) consecutive to the active edge of the second calibration signal (S21); S60) determining the phase difference depending on the parity of the number (n) of clock pulses.

Abstract: The invention relates to a method for synchronizing a plurality of analogue-digital or digital-analogue converters (CONV_k), the converters (CONV_k) all being connected to a control unit (UC), and to a clock (CLK) that has a predefined clock period (Tclk), the converters being also chained step-by-step so as to form a chain of converters, each converter (CONV_k) generating an internal synchronization signal (internal_sync_k) configured to supply a time reference on the transmission of data by the converter (CONV_k). The method allows the synchronization of the converters to be guaranteed using a process of learning and of configuration of the converters. The method allows any line distance constraint on the synchronization signal to be overcome.

Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the

Abstract: The present invention relates to a method for synchronizing digital data sent in series by a transmitter to a receiver, and to a device allowing such a method to be implemented. The invention aims to provide a method for synchronizing serial digital data without using a FIFO memory. The invented is based on the use of a single clock, in particular that of the receiver.

Abstract: Method for synchronizing digital data sent in series by a transmitter having a clock frequency freq1 to a receiver having a clock frequency freq2, comprising the steps a) to d) iterated until a stoppage condition is met and a step e): a) sending a digital datum from the transmitter to the receiver; b) generating N channels, each ith channel containing the datum, and being time shifted with respect to the (i?1)th channel, with N?3 and 2<i<N; c) sampling the N channels at the frequency freq2; d) comparing the N channels in groups of (2m+1) successive channels, m?1 and such that (2m+1)?N, and selecting groups of (2m+1) channels in which the data of these channels are identical in each iteration; e) selecting a channel belonging to the selected groups, the data contained in this channel being considered to be synchronized and in phase with the receiver and defining a variable P equal to the value i of the selected channel.