Patents by Inventor Quinn Gaumer

Quinn Gaumer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTERLACED CROSSTALK CONTROLLED TRACES, VIAS, AND CAPACITORS
    Publication number: 20230371169
    Abstract: A multilayer printed circuit board having a stackup including an upper half of the stackup and a lower half of the stackup, the multilayer printed circuit board having a top exposed surface and a bottom exposed surface, a first trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, a second trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, and first electrical components and second electrical components disposed on the top exposed surface of the multilayer printed circuit board and associated, respectively, with the first trace and via structure and the second trace and via structure, wherein the first electrical components are mounted orthogonally with respect to the second electrical components.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Shadi Ebrahimi Asl, Stephen Aubrey Scearce, Quinn Gaumer, Linda W. Scott
  • Interlaced crosstalk controlled traces, vias, and capacitors
    Patent number: 11785706
    Abstract: A multilayer printed circuit board having a stackup including an upper half of the stackup and a lower half of the stackup, the multilayer printed circuit board having a top exposed surface and a bottom exposed surface, a first trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, a second trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, and first electrical components and second electrical components disposed on the top exposed surface of the multilayer printed circuit board and associated, respectively, with the first trace and via structure and the second trace and via structure, wherein the first electrical components are mounted orthogonally with respect to the second electrical components.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 10, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Shadi Ebrahimi Asl, Stephen Aubrey Scearce, Quinn Gaumer, Linda W. Scott
  • INTERLACED CROSSTALK CONTROLLED TRACES, VIAS, AND CAPACITORS
    Publication number: 20220386452
    Abstract: A multilayer printed circuit board having a stackup including an upper half of the stackup and a lower half of the stackup, the multilayer printed circuit board having a top exposed surface and a bottom exposed surface, a first trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, a second trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, and first electrical components and second electrical components disposed on the top exposed surface of the multilayer printed circuit board and associated, respectively, with the first trace and via structure and the second trace and via structure, wherein the first electrical components are mounted orthogonally with respect to the second electrical components.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Inventors: Shadi Ebrahimi Asl, Stephen Aubrey Scearce, Quinn Gaumer, Linda W. Scott