Patents by Inventor Quyen Doan

Quyen Doan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240110481
    Abstract: A method of repairing a turbine blade includes positioning the turbine blade within a system including a machining tool; determining a first distance between a surface of a first PSP attached to a tip shroud of the turbine blade and a datum surface formed in the tip shroud; removing the first PSP from the tip shroud; coupling a second PSP to the tip shroud; and machining a surface of the second PSP using the machining tool, wherein machining the second PSP surface includes controlling movement of the machining tool using the datum surface as a reference, such that the machined second PSP surface is located the first distance from the datum surface.
    Type: Application
    Filed: September 27, 2023
    Publication date: April 4, 2024
    Inventors: Quyen Doan, Richard David Coen, Brently A. Lord
  • Patent number: 7999568
    Abstract: Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calibration block can transmit OCT control signals to one or multiple IO blocks. The IO blocks can be programmed to select OCT control signals from one of the calibration blocks. Enable signals enable one or more of the IO blocks to receive the selected OCT control signals. The OCT control signals are used to control the on-chip termination impedance at one or more IO buffers.
    Type: Grant
    Filed: May 24, 2008
    Date of Patent: August 16, 2011
    Assignee: Altera Corporation
    Inventors: Vikram Santurkar, Hyun Mo Yi, Quyen Doan
  • Patent number: 7410293
    Abstract: Techniques are provided for sensing the temperature of an integrated circuit (IC). A diode is provided on an IC. The voltage across the diode varies with the temperature of the IC. A feedback loop is coupled around the diode to monitor the voltage across the diode. The feedback loop contains a comparator and logic circuitry that outputs a digital code. The digital code varies in response to changes in the diode voltage. The value of the digital code can be used to determine the temperature on the IC. Techniques are also provided for automatically calibrating a temperature sensing circuit to compensate for inaccuracies caused by variations in process, temperature, and supply voltage. A calibration circuit is added to the feedback loop in the temperature sensor. The calibration circuit generates an offset code that is used to adjust the digital code to compensate for variations in temperature, process, and supply voltage.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: August 12, 2008
    Assignee: Altera Corporation
    Inventors: Vikram Santurkar, Quyen Doan
  • Patent number: 7391229
    Abstract: Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calibration block can transmit OCT control signals to one or multiple IO blocks. The IO blocks can be programmed to select OCT control signals from one of the calibration blocks. Enable signals enable one or more of the IO blocks to receive the selected OCT control signals. The OCT control signals are used to control the on-chip termination impedance at one or more IO buffers.
    Type: Grant
    Filed: February 18, 2006
    Date of Patent: June 24, 2008
    Assignee: Altera Corporation
    Inventors: Vikram Santurkar, Hyun Mo Yi, Quyen Doan
  • Patent number: 6462577
    Abstract: A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: October 8, 2002
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Christopher F. Lane, Srinivas T. Reddy, Brian D. Johnson, Ketan H. Zaveri, Mario Guzman, Quyen Doan