Abstract: A system includes a processor, a memory, a cache, program software, and a marker management engine. The software includes at least one marker. Each marker is a computer instruction and marks distinct computer code sections in the software. The engine (a) determines whether one of the at least one marker is executed during the execution of the program software, (b) monitors data accesses by the at least one processor to the at least one cache and the main memory, (c) stores at least one of the monitored data accesses in a pre-defined location in the main memory, and (d) optimizes only the computer code section indicated by the determined marker of the program software executed by the at least one processor based on the stored data accesses.

Abstract: A method of optimizing a computer program includes executing a program including a hint defined as a variable in program and providing within the program, and a marker instruction that receives the hint as a parameter. The marker instruction marks a section of the computer program for a subsequent optimization. During the execution of the computer program, and in response to the marker instruction being executed, a hardware engine monitors data accesses associated with execution of instructions in the marked section and stores the data accesses in the storage of the hint. A subsequent execution of the marked section of the computer program is optimized using the data stored in the storage of the hint.

Abstract: A exemplary system and method are provided for learning and cache management in software defined contexts. Exemplary embodiments of the present invention described herein address the problem of the data access wall resulting from processor stalls due to the increasing discrepancies between processor speed and the latency of access to data that is not stored in the immediate vicinity of the processor requesting the data.

Abstract: We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test (“FBIST”) mechanism for testing integrated circuits with internal memory state and complex transaction based interfaces. Such interfaces include system-on-chip applications, memory chip applications, and input/output (“IO”) protocol adapter chips.

Abstract: A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this (146,130) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.

Abstract: A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this (146,130) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.

Abstract: In a processing system having a main memory, wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies, a method and apparatus for providing compressed data integrity verification to insure detection of nearly any data corruption resulting from an anomaly anywhere in the logical processing or storage of compressed information. A cyclic redundancy code (CRC) is computed over a compressed data block as the data enters the compressor hardware, and the CRC is appended to the compressor output block before it is stored into the main memory. Subsequent read access results in comparing the CRC against a recomputation of the CRC as the block is uncompressed from the main memory. Any CRC miscompare implies an uncorrectable data error condition that may be used to interrupt the system operation.

Abstract: In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies and, wherein information stored within the main memory is indirectly accessible by a processor through an uncompressed information cache, an improved memory architecture, apparatus and method for detecting and recovering the main memory space used to store “stale” information associated with cache lines in the “modified” state, and returning the storage to an unused pool for use in storing other information. This improves the overall compression rate of the system, thus lessening the likelihood of encountering a “memory pressure” situation where the system runs low on unused memory.

Abstract: In a computer system, a system and methodology for dynamically allocating available physical memory to addressable memory space on an as needed basis, and to recover unused physical memory space when it is no longer needed. Physical memory is assigned to addressable memory space when that memory space is first written. When the system software determines it has no further need of a memory space, the physical memory is recovered and made available for reuse.