Abstract: An integrated semiconductor memory contains a multiplicity of bit line pairs which each comprise a first bit line and a second bit line. Sense amplifiers are each coupled to one of the bit line pairs for evaluating a signal on the first and second bit lines. A data line pair coupled to at least one of the multiplicity of bit line pairs for outputting a datum is furthermore provided. A correction device is connected on the output side to the data line pair or to at least one bit line pair. The device is embodied for feeding a correction signal onto the line pair.

Abstract: An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.

Abstract: An integrated circuit memory device includes a memory array with associated word lines and bit lines. A switching arrangement is connected between a word line and a first voltage source that selectively connects the word line to the first voltage source, and also is responsive to a short-circuit between the word line and the bit line.

Abstract: In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration.

Abstract: A voltage level converter device for the conversion of an input signal, which is at a first voltage level, into an output signal, which is at a second voltage level that differs from the first voltage level, where the voltage level converter device has at least one transistor, and in which an additional transistor, controlled by a control signal at a voltage level corresponding to that of the input signal, is provided in a current path that is to be accordingly switched on or off when the output signal switches over for switching that path on or off.

Abstract: In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration.