Patents by Inventor R. Justice

R. Justice has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11080605
    Abstract: Systems and techniques for interest matched interaction initialization are described herein. A first set of profile attributes for a first user and second set of profile attributes for a second user may be obtained. A first set of data sources and a second set of data sources may be identified respectively using the first set and second set of profile attributes. A first dataset and a second dataset may be collected respectively using the first and second set of data sources. An interest vector model may be generated using data elements of the first dataset based on an interest identified in the first dataset. The second dataset may be evaluated using the interest vector model to identify the interest as a shared interest in the second dataset. An interaction initialization item may be generated by identifying content associated with the shared interest. The interaction initialization item may be transmitted to a device.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 3, 2021
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Chad Allen Yarbrough, John C. Brenner, Jeniffer R. Justice, Gwendoria M. Salley, Zachary Scott Miinch, James D. Cahill
  • Publication number: 20160176742
    Abstract: A system of treating discharge water from a National Pollution Discharge Elimination Systems (NPDES) by utilizing naturally occurring groundwater containing increased levels of naturally occurring chemical or mineral elements or compounds as a catalyst to induce a reaction with the non-compliant chemical or mineral element or compound of the discharge water, resulting in a reduction of the discharge contaminate to a level which does not exceed state or federal water quality standards.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 23, 2016
    Inventors: Jeremy S. Starks, Joshua R. Justice, Chris W. White, Anthony J. White, Jeffery W. Allen
  • Patent number: 8705529
    Abstract: A message processing engine may intercept outgoing and incoming messages by bridging an interface between a virtual network interface and a physical network interface. The message processing engine may have a raw packet analyzer that may determine if a packet is to be processed based on a policy, and then may decode the packet using a first set of protocols, perform a translation in the decoded state, then encode the packet using the same or a different set of protocols. The message processing engine may be used to perform translations to enable two otherwise incompatible devices to communicate as well as apply various protocols including security protocols to communications with another device similarly configured. In many embodiments, the raw packet analyzer may be a service with administrative privileges, but the decoder, encoder, and translator may be operated with user privileges.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 22, 2014
    Assignee: Microsoft Corporation
    Inventors: Nicholas Alexander Allen, John R Justice
  • Patent number: 8510343
    Abstract: User experience in a designer tool manages cogeneration of a database application and a database accessible through the application. A user places a visual representation of an application element designed to control a relational or hierarchical dataset. Code is automatically called to add the application element to the application, and automatically invoked to create database schema elements designed to implement the dataset in the database under application element control. Users verify that an application element has been automatically added, and confirm that database schema elements implementing the dataset(s) under control of the application element have been automatically created. A tutorial illustrates a workflow utilizing a designer tool to cogenerate a database application and a database without a data design step. A wizard utilizes the designer tool to cogenerate a database application and a database that collectively implement a calendar, a diagram, a tree, a wiki, and/or a list.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: August 13, 2013
    Assignee: Microsoft Corporation
    Inventors: Gersh Payzer, Stephen Michael Danton, Noaa Avital, Pedro Ardila, Stephen J. Millet, John R. Justice, Eric Kenneth Zinda, Christopher L. Anderson
  • Publication number: 20120327934
    Abstract: A message processing engine may intercept outgoing and incoming messages by bridging an interface between a virtual network interface and a physical network interface. The message processing engine may have a raw packet analyzer that may determine if a packet is to be processed based on a policy, and then may decode the packet using a first set of protocols, perform a translation in the decoded state, then encode the packet using the same or a different set of protocols. The message processing engine may be used to perform translations to enable two otherwise incompatible devices to communicate as well as apply various protocols including security protocols to communications with another device similarly configured. In many embodiments, the raw packet analyzer may be a service with administrative privileges, but the decoder, encoder, and translator may be operated with user privileges.
    Type: Application
    Filed: July 30, 2012
    Publication date: December 27, 2012
    Applicant: MICROSOFT CORPORATION
    Inventors: Nicholas Alexander Allen, John R. Justice
  • Patent number: 8254381
    Abstract: A message processing engine may intercept outgoing and incoming messages by bridging an interface between a virtual network interface and a physical network interface. The message processing engine may have a raw packet analyzer that may determine if a packet is to be processed based on a policy, and then may decode the packet using a first set of protocols, perform a translation in the decoded state, then encode the packet using the same or a different set of protocols. The message processing engine may be used to perform translations to enable two otherwise incompatible devices to communicate as well as apply various protocols including security protocols to communications with another device similarly configured. In many embodiments, the raw packet analyzer may be a service with administrative privileges, but the decoder, encoder, and translator may be operated with user privileges.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: August 28, 2012
    Assignee: Microsoft Corporation
    Inventors: Nicholas Alexander Allen, John R Justice
  • Publication number: 20110307519
    Abstract: User experience in a designer tool manages cogeneration of a database application and a database accessible through the application. A user places a visual representation of an application element designed to control a relational or hierarchical dataset. Code is automatically called to add the application element to the application, and automatically invoked to create database schema elements designed to implement the dataset in the database under application element control. Users verify that an application element has been automatically added, and confirm that database schema elements implementing the dataset(s) under control of the application element have been automatically created. A tutorial illustrates a workflow utilizing a designer tool to cogenerate a database application and a database without a data design step. A wizard utilizes the designer tool to cogenerate a database application and a database that collectively implement a calendar, a diagram, a tree, a wiki, and/or a list.
    Type: Application
    Filed: June 11, 2010
    Publication date: December 15, 2011
    Applicant: MICROSOFT CORPORATION
    Inventors: Gersh Payzer, Stephen Michael Danton, Noaa Avital, Pedro Ardila, Stephen J. Millet, John R. Justice, Eric Kenneth Zinda, Christopher L. Anderson
  • Publication number: 20090190585
    Abstract: A message processing engine may intercept outgoing and incoming messages by bridging an interface between a virtual network interface and a physical network interface. The message processing engine may have a raw packet analyzer that may determine if a packet is to be processed based on a policy, and then may decode the packet using a first set of protocols, perform a translation in the decoded state, then encode the packet using the same or a different set of protocols. The message processing engine may be used to perform translations to enable two otherwise incompatible devices to communicate as well as apply various protocols including security protocols to communications with another device similarly configured. In many embodiments, the raw packet analyzer may be a service with administrative privileges, but the decoder, encoder, and translator may be operated with user privileges.
    Type: Application
    Filed: January 28, 2008
    Publication date: July 30, 2009
    Applicant: MICROSOFT CORPORATION
    Inventors: Nicholas Alexander Allen, John R. Justice
  • Patent number: 7453875
    Abstract: A sending computer system can identify one or more available network resources at one or more network computers by sending a request for services using Simple Object Access Protocol (SOAP) over User Datagram Protocol (UDP). In particular, the sending computer system prepares a SOAP message that includes a request for available resources. The sending computer system then encapsulates the SOAP message into a user datagram, and sends the user datagram to one or more identifiable computer systems on the network. In one implementation, the sending computer system sends the user datagram to a multi-cast Uniform Resource Identifier (URI). The receiving computer system receives the message through UDP, unpacks the message, and responds to the SOAP message request. Accordingly, the sending computer system can query multiple computer systems in an efficient manner without necessarily incurring the overhead otherwise associated with connection-oriented communication.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: November 18, 2008
    Assignee: Microsoft Corporation
    Inventors: Michael S. Vernal, Erik B. Christensen, Martin Gudgin, John R. Justice, Gopal Kakivaya, David Langworthy, Yaniv Pessach, Jeffrey Schlimmer, Elliot Waingold, Kenneth D. Wolf
  • Patent number: 7072421
    Abstract: A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The phase locked loop that is responsive to the modulated signal includes a controlled oscillator output and a feedback loop between the controlled oscillator input and the controlled oscillator output. The feedback loop includes a mixer that is responsive to a local oscillator. The modulator may be placed in the phase locked loop.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: July 4, 2006
    Assignee: Telefonaktiebolaget L.M. Ericsson
    Inventors: Erik Bengtsson, Aristotle Hadjichristos, Scott R. Justice
  • Publication number: 20060097553
    Abstract: Embodiments of a seating module system are described. In one embodiment, a seating module may include a central keel defining opposite aisle and window side areas and opposite fore and aft ends. The seating module may also have an aisle seat and an aisle footstool located in the aisle side area. The seating module may further include a window seat and a window footstool located in the window side area. The window seat may be in a staggered relationship with the aisle seat with the window seat positioned closer towards the fore end than the aisle seat. The seating module may also include a privacy screen that comprises an window seat portion and an aisle seat portion. The window seat portion of the privacy screen may extend along the central keel and between the window seat and the window footstool.
    Type: Application
    Filed: September 7, 2005
    Publication date: May 11, 2006
    Inventors: David Spurlock, R. Justice
  • Patent number: 6975686
    Abstract: A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The in-phase and quadrature-phase signals may be normalized in-phase and quadrature-phase signals. Alternatively, a phase tracking subsystem may be provided that is responsive to the quadrature modulator to produce a phase signal that is responsive to phase changes in the modulated signal and that is independent of amplitude changes in the modulated signal.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: December 13, 2005
    Assignee: Telefonaktiebolaget L.M. Ericsson
    Inventors: M. Ali Khatibzadeh, Aristotle Hadjichristos, Scott R. Justice, Steven G. Cairns, Charles Gore, Jr., Jeffrey Schlang, Erik Bengtsson, William O. Camp, Jr., David R. Pehlke
  • Patent number: 6909757
    Abstract: Embodiments of methods, transmitters, and computer program products are provided for transmitting a signal by adjusting a delay between an amplitude component of the signal and a phase component of the signal based on the transmission power. Error vector magnitude and adjacent channel power ratio are two common criteria used in evaluating transmitter performance. By adjusting the delay between the amplitude component of the transmitted signal and the phase component of the transmitted signal, the error vector magnitude and/or the adjacent channel power ratio may be reduced. The particular delay value that provides the best error vector magnitude performance and/or adjacent channel power ratio performance may differ based on the transmission power level. Therefore, the delay value is adjusted based on the transmission power.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: June 21, 2005
    Assignee: Ericsson Inc.
    Inventors: Scott R. Justice, Erik L. Bengtsson, David R. Pehlke
  • Patent number: 6829595
    Abstract: A method for authenticating internet billing using a third party account server. Internet users maintain authentication information such as user PIN codes with a third party account server. An internet user seeking to purchase from and an internet vendor is linked to a third party account server and transmits the appropriate authentication information to the account server for approval. The account server then approves or disapproves the transaction based on the validity of the authentication information that it receives from the user.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: December 7, 2004
    Assignee: Valista, Inc.
    Inventor: James R. Justice
  • Publication number: 20020168020
    Abstract: Embodiments of methods, transmitters, and computer program products are provided for transmitting a signal by adjusting a delay between an amplitude component of the signal and a phase component of the signal based on the transmission power. Error vector magnitude and adjacent channel power ratio are two common criteria used in evaluating transmitter performance. By adjusting the delay between the amplitude component of the transmitted signal and the phase component of the transmitted signal, the error vector magnitude and/or the adjacent channel power ratio may be reduced. The particular delay value that provides the best error vector magnitude performance and/or adjacent channel power ratio performance may differ based on the transmission power level. Therefore, the delay value is adjusted based on the transmission power.
    Type: Application
    Filed: May 14, 2001
    Publication date: November 14, 2002
    Inventors: Scott R. Justice, Erik L. Bengtsson, David R. Pehlke
  • Patent number: 6424229
    Abstract: Voltage controlled oscillator circuits are provided including a voltage controlled oscillator (VCO) having an input and an output responsive to the input. A tuning circuit coupled to the VCO sets a relationship between the input and the output of the VCO. An aided acquisition circuit is coupled to the input of the VCO. A control circuit selects a state of the tuning circuit to set the relationship between the input and the output of the VCO. The control circuit also controls operation of the aided acquisition circuit responsive to changes in the state of the tuning circuit. Methods for operating voltage controlled oscillator circuits are also provided. In addition, phase lock loop circuits and mobile terminals including the voltage controlled oscillator circuits are provided.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: July 23, 2002
    Assignee: Ericsson Inc.
    Inventors: Scott R. Justice, Erik L. Bengtsson
  • Publication number: 20020071497
    Abstract: A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The phase locked loop that is responsive to the modulated signal includes a controlled oscillator output and a feedback loop between the controlled oscillator input and the controlled oscillator output. The feedback loop includes a mixer that is responsive to a local oscillator. The modulator may be placed in the phase locked loop.
    Type: Application
    Filed: December 22, 2000
    Publication date: June 13, 2002
    Inventors: Erik Bengtsson, Aristotle Hadjichristos, Scott R. Justice
  • Patent number: 6366162
    Abstract: An input buffer circuit is operable to selectively present either low or high input impedance while maintaining uniform output impedance. The buffer is characterized by first and second amplifier circuits connected in parallel between an input to and an output from the buffer. The amplifiers are individually controlled between enabled and disabled states. When enabled, the first amplifier has low input impedance and predetermined output impedance and the second amplifier has high input impedance and the predetermined output impedance, and when disabled each amplifier has high input and output impedance. To operate the buffer to have low input impedance, the first amplifier is enabled while the second amplifier is disabled. To operate the buffer to have high input impedance, the second amplifier is enabled while the first amplifier is disabled.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: April 2, 2002
    Assignee: Ericsson Inc.
    Inventors: Chris W. Angell, Erik L. Bengtsson, Scott R. Justice, Aristotele Hadjichristos
  • Publication number: 20010049630
    Abstract: When a consumer initiates a MicroTrac account, they will be prompted to choose a password (PIN) protection for different types of vendor sites.
    Type: Application
    Filed: June 26, 1998
    Publication date: December 6, 2001
    Inventor: JAMES R. JUSTICE
  • Patent number: 6078219
    Abstract: A wide range single stage variable gain amplifier is provided for receiving an input signal and outputting an amplitude varied version of the received input signal. In its most basic form, the wide range single stage variable gain amplifier includes an input circuit receiving an input signal and developing an input current, a first control circuit receiving the input current, the first control circuit being selectively controllable to output an attenuated version of the received input current, a second control circuit directly connected to the first control circuit for receiving the attenuated input current therefrom, the second control circuit being selectively controllable to output a further attenuated version of the attenuated input current, and an output circuit receiving the further attenuated input current and developing an amplitude varied version of the received input signal.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: June 20, 2000
    Assignee: Ericsson Inc.
    Inventors: Aristotele Hadjichristos, Scott R. Justice