Abstract: A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.

Abstract: An integrated electroosmotic pump may be incorporated in the same integrated circuit package with a re-combiner, and an integrated circuit chip to be cooled by fluid pumped by the electroosmotic pump.

Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing micro-channels or micro-trenches, and a technique for fabricating the same.

Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.

Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

Abstract: Method and structure for vertically stacking microelectronic devices are disclosed. Subsequent to appropriate deposition, patterning, trenching, and passivation subprocesses, a conductive layer is formed wherein one end comprises an external contact portion for C4 interfacing, and another end establishes electrical contact with an internal contact at the bonding interface between the two interfaced devices. The conductive layer may be formed using electroplating, and may be formed in a single electroplating treatment, to form a continuous structure from via portion to external contact portion.

Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.

Abstract: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Abstract: According to one embodiment a method is disclosed. The method includes applying a photoresist layer to a first wafer, etching the first wafer, bonding the first wafer to a second wafer and thinning the first wafer; wherein an unsupported bevel portion of the first wafer is removed.

Abstract: Method and structure for optimizing and controlling diffusional creep at metal contact interfaces are disclosed. Embodiments of the invention accommodate height variations in adjacent contacts, decrease planarization uniformity requirements, and facilitate contact bonding at lower temperatures and pressures by employing shapes and materials that respond predictably to compressive interfacing loads.

Abstract: Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The vias used for the backside connections are formed on a side of the first wafer along with an interconnect structure, and the backside connections are formed on an opposing side of the first wafer using these vias.

Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.

Abstract: A device where the electrodes of an electroosmotic pump are located directly in the flow-producing region of the electroosmotic pump is described as well as methods of forming such a device. Placing the electrodes of an electroosmotic pump directly in the flow-producing region of the electroosmotic pump may increase the flow rate of a cooling fluid that is pumped through the pump. The cooling fluid may then remove a greater amount of heat from the substrate over which it is flowed. The substrate may be the non-device side of a die or a thermal management chip that is placed in direct contact with the non-device side of a die. In these instances the electroosmotic pump may be part of a microelectronic package containing the die or the thermal management chip.

Abstract: An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Abstract: A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.

Abstract: A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.