Patents by Inventor R. Marshall Stowell
R. Marshall Stowell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10351968Abstract: Apparatus and methods for electroplating are described. Apparatus described herein include anode supports including positioning mechanisms that maintain a consistent distance between the surface of the wafer and the surface of a consumable anode during plating. Greater uniformity control is achieved. The consumable anode in one implementation has a plurality of through channels and at least one depression on its surface (e.g., a depression surrounding a channel) that is configured for registering with a protrusion on a component of an anode assembly, such as with a support plate. Fasteners may pass through the channels in the anode and attach it to a charge plate.Type: GrantFiled: April 7, 2016Date of Patent: July 16, 2019Assignee: Novellus Systems, Inc.Inventors: Jingbin Feng, R. Marshall Stowell, Shantinath Ghongadi, Zhian He, Frederick Dean Wilmot
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Patent number: 9677188Abstract: The disclosed embodiments relate to methods and apparatus for immersing a substrate in electrolyte in an electroplating cell under sub-atmospheric conditions to reduce or eliminate the formation/trapping of bubbles as the substrate is immersed. Various electrolyte recirculation loops are disclosed to provide electrolyte to the plating cell. The recirculation loops may include pumps, degassers, sensors, valves, etc. The disclosed embodiments allow a substrate to be immersed quickly, greatly reducing the issues related to bubble formation and uneven plating times during electroplating.Type: GrantFiled: December 10, 2013Date of Patent: June 13, 2017Assignee: Novellus Systems, Inc.Inventors: R. Marshall Stowell, Jingbin Feng, David W. Porter
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Publication number: 20160222541Abstract: Apparatus and methods for electroplating are described. Apparatus described herein include anode supports including positioning mechanisms that maintain a consistent distance between the surface of the wafer and the surface of a consumable anode during plating. Greater uniformity control is achieved.Type: ApplicationFiled: April 7, 2016Publication date: August 4, 2016Inventors: Jingbin Feng, R. Marshall Stowell, Shantinath Ghongadi, Zhian He, Frederick Dean Wilmot
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Patent number: 9340893Abstract: Apparatus and methods for electroplating are described. Apparatus described herein include anode supports including positioning mechanisms that maintain a consistent distance between the surface of the wafer and the surface of a consumable anode during plating. Greater uniformity control is achieved.Type: GrantFiled: April 3, 2015Date of Patent: May 17, 2016Assignee: Novellus Systems, Inc.Inventors: Jingbin Feng, R. Marshall Stowell, Shantinath Ghongadi, Zhian He, Frederick Dean Wilmot
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Publication number: 20150211144Abstract: Apparatus and methods for electroplating are described. Apparatus described herein include anode supports including positioning mechanisms that maintain a consistent distance between the surface of the wafer and the surface of a consumable anode during plating. Greater uniformity control is achieved.Type: ApplicationFiled: April 3, 2015Publication date: July 30, 2015Inventors: Jingbin Feng, R. Marshall Stowell, Shantinath Ghongadi, Zhian He, Frederick Dean Wilmot
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Patent number: 9028657Abstract: Apparatus and methods for electroplating are described. Apparatus described herein include anode supports including positioning mechanisms that maintain a consistent distance between the surface of the wafer and the surface of a consumable anode during plating. Greater uniformity control is achieved.Type: GrantFiled: September 10, 2010Date of Patent: May 12, 2015Assignee: Novellus Systems, Inc.Inventors: Jingbin Feng, R. Marshall Stowell, Shantinath Ghongadi, Zhian He, Frederick Dean Wilmot
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Publication number: 20140097088Abstract: The disclosed embodiments relate to methods and apparatus for immersing a substrate in electrolyte in an electroplating cell under sub-atmospheric conditions to reduce or eliminate the formation/trapping of bubbles as the substrate is immersed. Various electrolyte recirculation loops are disclosed to provide electrolyte to the plating cell. The recirculation loops may include pumps, degassers, sensors, valves, etc. The disclosed embodiments allow a substrate to be immersed quickly, greatly reducing the issues related to bubble formation and uneven plating times during electroplating.Type: ApplicationFiled: December 10, 2013Publication date: April 10, 2014Applicant: Novellus Systems, Inc.Inventors: R. Marshall Stowell, Jingbin Feng, David W. Porter
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Patent number: 8470191Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.Type: GrantFiled: August 6, 2007Date of Patent: June 25, 2013Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
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Patent number: 8415261Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: October 11, 2011Date of Patent: April 9, 2013Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 8257781Abstract: A main reservoir holds cool reactant liquid. A reaction vessel for treating a substrate is connected to the main reservoir by a feed conduit. A heater is configured to heat reactant liquid in the feed conduit before the liquid enters the reaction vessel. Preferably, the heater is a microwave heater. A recycle conduit connects the reaction vessel with the main reservoir. Preferably, a recycle cooler cools reactant liquid in the recycle conduit before the liquid returns to the main reservoir. Preferably, an accumulation vessel is integrated in the feed conduit for accumulating, heating, conditioning and monitoring reactant liquid before it enters the reaction vessel. Preferably, a recycle accumulator vessel is integrated in the recycle conduit to accommodate reactant liquid as it empties out of the reaction vessel.Type: GrantFiled: August 11, 2005Date of Patent: September 4, 2012Assignee: Novellus Systems, Inc.Inventors: Eric G. Webb, Steven T. Mayer, David Mark Dinneen, Edmund B. Minshall, Christopher M. Bartlett, R. Marshall Stowell, Mark T. Winslow, Avishai Kepten, Jingbin Feng, Norman D. Kaplan, Richard K. Lyons, John B. Alexy
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Patent number: 8158532Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.Type: GrantFiled: November 20, 2006Date of Patent: April 17, 2012Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
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Publication number: 20120061246Abstract: Apparatus and methods for electroplating are described. Apparatus described herein include anode supports including positioning mechanisms that maintain a consistent distance between the surface of the wafer and the surface of a consumable anode during plating. Greater uniformity control is achieved.Type: ApplicationFiled: September 10, 2010Publication date: March 15, 2012Inventors: Jingbin Feng, R. Marshall Stowell, Shantinath Ghongadi, Zhian He, Frederick Dean Wilmot
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Patent number: 8043958Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: September 3, 2010Date of Patent: October 25, 2011Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 7811925Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: July 31, 2008Date of Patent: October 12, 2010Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 7690324Abstract: During fluid treatment of a substrate surface, a carrier/wafer assembly containing a substrate wafer closes the top of a microcell container. The carrier/wafer assembly and the container walls define a thin enclosed treatment volume that is filled with treating fluid, such as electroless plating solution. The thin fluid-treatment volume typically has a volume in a range of about from 100 ml to 500 ml. Preferably a container is heated and the treating fluid is pre-heated before being injected into the container. Preferably, the chemical composition, temperature, and other properties of fluid in the thin enclosed fluid-treatment volume are dynamically variable. A rinse shield and a rinse nozzle are located above the container. A carrier/wafer assembly in a rinse position substantially closes the top of the rinse shield.Type: GrantFiled: August 9, 2005Date of Patent: April 6, 2010Assignee: Novellus Systems, Inc.Inventors: Jingbin Feng, Steven T. Mayer, Daniel Mark Dinneen, Edmund B. Minshall, Christopher M. Bartlett, Eric G. Webb, R. Marshall Stowell, Mark T. Winslow, Avishai Kepten, Norman D. Kaplan, Richard K. Lyons, John B. Alexy
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Publication number: 20090280649Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.Type: ApplicationFiled: August 6, 2007Publication date: November 12, 2009Applicant: Novellus Systems, Inc.Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
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Publication number: 20090277867Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.Type: ApplicationFiled: November 20, 2006Publication date: November 12, 2009Applicant: Novellus Systems, Inc.Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
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Patent number: 7605082Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: October 13, 2005Date of Patent: October 20, 2009Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 6964792Abstract: The present invention provides apparatus and methods for controlling flow dynamics of a plating fluid during a plating process. The invention achieves this fluid control through use of a diffuser membrane. Plating fluid is pumped through the membrane; the design and characteristics of the membrane provide a uniform flow pattern to the plating fluid exiting the membrane. Thus a work piece, upon which a metal or other conductive material is to be deposited, is exposed to a uniform flow of plating fluid.Type: GrantFiled: August 10, 2001Date of Patent: November 15, 2005Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, R. Marshall Stowell, Evan E. Patton, Seshasayee Varadarajan
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Patent number: 6815349Abstract: An apparatus for holding work pieces during electroless plating has certain improved features designed for use at relatively high temperatures (e.g., at least about 50 degrees C.). Cup and cone components of a “clamshell” apparatus that engage a work piece are made from dimensionally stable materials with relatively low coefficients of thermal expansion. Further, O-rings are removed from positions that come in contact with the work piece. This avoids the difficulty caused by O-rings sticking to work piece surfaces during high temperature processing. In place of the O-ring, a cantilever member is provided on the portion of the cone that contacts the work piece. Still further, the apparatus makes use of a heat transfer system for controlling the temperature of the work piece backside during plating.Type: GrantFiled: October 18, 2002Date of Patent: November 9, 2004Assignee: Novellus Systems, Inc.Inventors: Edmund B. Minshall, Kevin Biggs, R. Marshall Stowell, Wayne Fetters