Abstract: A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N?2, M?2, K?2, and B?1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.

Abstract: A method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N?2, M?2, K?2, and B?1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.

Abstract: A processor and method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N?2, M?2, K?1, and B?1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.

Abstract: A graphics system comprising a format processor for receiving display data including pixel data and color-blending information for at least two (2) separate display layers, a color blender and color processors. The pixel data includes color information for the display layers. The color-blending information determines weighting factors for use in blending the colors of the display layers. The format processor outputs separate streams of pixel data, one for each display layer, as well as the weighting factors. Each stream of pixel data outputted by the processor is inputted into a corresponding color processor that assigns colors to a particular display layer according to the color information in the corresponding pixel data. The color blender blends the colors assigned to the display layers according to the weighting factors.

Abstract: Method and apparatus for adjusting the color of the sprite in display systems, so that the sprite is always distinctively visible irrespective of the underlying displayed data. A palette DAC of a display system is provided with sprite control logic, which derives the color of a sprite to be overlaid on an image displayed on a video display unit of a display system by inverting only the most significant bit (MSB) of each of the red, green and blue pixel data components of the underlying image. In a preferred embodiment, the sprite control logic circuit comprises first, second and third multiplexors (MUXes) each having a first input connected to receive the MSB of the red, green and blue pixel data components of the underlying image, respectively, and a second input connected to receive the output of first, second and third XOR gates, respectively.