Abstract: An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel processing system comprises an instruction folding mechanism and a pixel shader. The instruction folding mechanism folds a plurality of first instructions in a first program to generate a second program having at least one second instruction which is a combination of the first instructions. The pixel shader connected to the instruction folding mechanism fetches the second program to decode at least the second instruction having the combination of the first instructions to execute the second program. The instruction folding mechanism comprises an instruction scheduler, a folding rule checker, and an instruction combiner. The instruction scheduler connected to the folding rule checker is used to scan the first instructions according to static positions in order to schedule the first instructions in the first program.

Abstract: A touch position detecting method for a touch screen is disclosed. In the method, a specific point is detected by comparing a sensed data thereof with a first threshold and by comparing a sum of sensed values of a group of points which include the specific point with a second threshold. Furthermore, the sensed value of the specific point is checked to see if it is the maximum among the group of points. By using such a method, accuracy of touch position detection can be improved.

Abstract: A hierarchical sensing method for a touch panel is disclosed. The touch panel has a matrix of points for detecting a touch or touches. The method includes dividing the points into a plurality of blocks; sensing first data from the respective blocks; determining which one or ones of the blocks are touched blocks according to the first data; sensing second data from each point of the touched blocks; and determining which one or ones of the points are touched points according to the second data. By using the method of the present invention, fast sensing speed and high sensing accuracy can be both achieved.

Abstract: Methods, systems, and apparatuses, including computer programs encoded on computer-readable medium, including an instruction scheduler for scanning first and second instructions that are operable to output data to different components in a register. A rule checker determines if the scanned first and second instructions are data independent. An instruction combiner, in response to a determination that the scanned first and second instructions are data independent, forms a combination of the scanned first and second instructions. A processing unit that includes a single decoder, receives the combination, decodes the combination using the single decoder, and executes the combination.

Abstract: An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel processing system comprises an instruction folding mechanism and a pixel shader. The instruction folding mechanism folds a plurality of first instructions in a first program to generate a second program having at least one second instruction which is a combination of the first instructions. The pixel shader connected to the instruction folding mechanism fetches the second program to decode at least the second instruction having the combination of the first instructions to execute the second program. The instruction folding mechanism comprises an instruction scheduler, a folding rule checker, and an instruction combiner. The instruction scheduler connected to the folding rule checker is used to scan the first instructions according to static positions in order to schedule the first instructions in the first program.

Abstract: The present invention discloses a texture filtering system, comprising a sequence generator, a retrieve unit and a dispatch unit. The sequence generator generates an execution sequence in each duty cycle. The execution sequence is the priority of respectively retrieving multiple pixels from multiple queues. The retrieve unit outputs multiple Boolean signals based on the limitation of the total number of all-purpose texture filters and the above priority in a duty cycle for determining from which queues the pixels are retrieved to perform a texture filtering process, and the dispatch unit assigns the multiple texture filter formats of the pixels to be processed and the anisotropic ratios thereof to multiple address generators.

Abstract: A pixel processing system includes a register-collecting mechanism and a pixel shader. The register-collecting mechanism corrects a first program to a second program. The first program requires a number of first registers. The second program requires a portion of the first registers of the first program. The pixel shader executes the second program. A method for register-collecting mechanism comprises the steps of: scanning the first instructions of the first program; decoding the first instructions to obtaining a plurality of first register numbers of busy register group of the first program; correcting the first program to a second program which only occupies the busy register group. As a result, the idle register group of the first program is available to be reallocated to the additional piled in pixels. Thus the pixel processing system can process more pixels in a batch using a given number of registers, and longer texture load latency can be hidden.

Abstract: The present invention discloses re-configurable data transmission ports with data-integrity transaction controlling unit in a computerized computer and the method for performing the same. The controlling unit further includes a port-configuration detecting mechanism and a buffer-configuration subunit. The port-configuration detecting mechanism can inspect configuration status of all of the first ports on variance of data transmission bandwidths, e.g. “merge” or “spilt” status. The buffer-configuration subunit upon different configuration status of each first port configures each retry buffer. When a specific first port is configured on “merge” status, the buffer-configuration subunit can follows up to configure the retry buffer owned by the specific first port and the retry buffers owned but disused by the other first ports to constitute a buffer group with merging of storing spaces of said configured retry buffers.

Abstract: An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel processing system comprises an instruction folding mechanism and a pixel shader. The instruction folding mechanism folds a plurality of first instructions in a first program to generate a second program having at least one second instruction which is a combination of the first instructions. The pixel shader connected to the instruction folding mechanism fetches the second program to decode at least the second instruction having the combination of the first instructions to execute the second program. The instruction folding mechanism comprises an instruction scheduler, a folding rule checker, and an instruction combiner. The instruction scheduler connected to the folding rule checker is used to scan the first instructions according to static positions in order to schedule the first instructions in the first program.

Abstract: An alpha-to-coverage transformation is performed by a pixel shader. The pixel shader compares data of a transparency column of a pixel and thresholds of sub-pixels of the pixel to generate a plurality of coverage masks, and stores the plurality of coverage masks in the LSBs of the transparency column of the pixel, and finally update the data of the sub-pixels according to the coverage masks stored in the transparency column of the pixel. A new instruction “a2c” is invented to speed up such thresholds comparison and coverage mask generation.

Abstract: An early retiring instruction mechanism, a method for performing the early retiring instruction mechanism and a pixel processing system employing the early retiring instruction mechanism applied to a graphic processor unit (GPU) are described. The pixel processing system comprises an early retiring instruction mechanism and a pixel shader. The early retiring instruction mechanism selectively retires a plurality of instructions in a first program in order to generate at least one early retiring instruction in a second program. The pixel shader is connected to the early retiring instruction mechanism. The pixel shader fetches the second program and decodes at least one early retiring instruction to execute the second program therein for processing a plurality of pixels. Then, the pixel shader checks whether the pixels in the process of the early retiring instruction generated from early retiring instruction mechanism are directly issued to leave the pixel shader in advance.

Abstract: An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel processing system comprises an instruction folding mechanism and a pixel shader. The instruction folding mechanism folds a plurality of first instructions in a first program to generate a second program having at least one second instruction which is a combination of the first instructions. The pixel shader connected to the instruction folding mechanism fetches the second program to decode at least the second instruction having the combination of the first instructions to execute the second program. The instruction folding mechanism comprises an instruction scheduler, a folding rule checker, and an instruction combiner. The instruction scheduler connected to the folding rule checker is used to scan the first instructions according to static positions in order to schedule the first instrictions in the first program.

Abstract: The present provides an instruction removing mechanism and a method using the same. The instruction removing mechanism is capable of scanning a graphic program to determine whether there is any simple texture load instruction (texld instruction) in the program. The simple texld instructions will be transmitted directly to the texture unit and deleted from a texld instruction collector to prevent the pixel shader executing the simple texld instructions before the texture unit.

Abstract: A pixel processing system includes a register-collecting mechanism and a pixel shader. The register-collecting mechanism corrects a first program to a second program. The first program requires a number of first registers. The second program requires a portion of the first registers of the first program. The pixel shader executes the second program. A method for register-collecting mechanism comprises the steps of: scanning the first instructions of the first program; decoding the first instructions to obtaining a plurality of first register numbers of busy register group of the first program; correcting the first program to a second program which only occupies the busy register group. As a result, the idle register group of the first program is available to be reallocated to the additional piled in pixels. Thus the pixel processing system can process more pixels in a batch using a given number of registers, and longer texture load latency can be hidden.

Abstract: A method for PCI Express Power Management using a PCI PM mechanism in a computer system. The computer system includes a PCI PME (Power Management Event) controller and a PCI Express Root Complex. The method includes converting a Beacon signal generated by the PCI Express Root Complex into a Pseudo-PME signal, the Beacon signal asserting the Pseudo-PME signal. A Pseudo-PME line electrically connected with an PME input of the PCI PME controller and the PCI Express Root Complex is provided for transmitting the Pseudo-PME signal to the PCI PME controller. The PME input receives PME signals generated by PCI-compliant devices through a PCI Bus of the computer system. Before the computer system is under the control of an operating system, the Pseudo-PME signal is de-asserted.

Abstract: A method for PCI ExpressPower Management using a PCI PM mechanism in a computer system. The computer system includes a PCI PME (Power Management Event) controller and a PCI Express Root Complex. The method includes converting a plurality of PM_PME packets generated by the PCI Express Root Complex into a Pseudo-PME signal, a first PM_PME packet of the plurality of PM_PME packets asserting the Pseudo-PME signal. A Pseudo-PME line electrically connected with a PME input of the PCI PME controller and the PCI Express Root Complex is provided for transmitting the Pseudo-PME signal to the PCI PME controller. The PME input receives PME signals generated by PCI-compliant devices through a PCI Bus of the computer system. The method further includes de-asserting the Pseudo-PME signal. The de-assertion of the Pseudo-PME signal follows the assertion of the Pseudo-PME signal by a predetermined time interval.

Abstract: A register-collecting mechanism and method using the same for multi-threaded processors are described. The register-collecting mechanism includes an instruction scanner, a register mapping table, an instruction modifier and an indication reporter. The instruction scanner scans one or more first programs having a plurality of first instructions and decode each of the first instructions to extract a plurality of nominal register numbers from the first instructions. The register mapping table compares the nominal register numbers of the first instructions to determine whether to collect a plurality of physical register numbers in sequence of register numbers when at least one of the nominal register numbers is unmapped with respective physical register number previously stored within the register mapping table.

Abstract: The present invention discloses re-configurable data transmission ports with data-integrity transaction controlling unit in a computerized computer and the method for performing the same. The controlling unit further includes a port-configuration detecting mechanism and a buffer-configuration subunit. The port-configuration detecting mechanism can inspect configuration status of all of the first ports on variance of data transmission bandwidths, e.g. “merge” or “spilt” status. The buffer-configuration subunit upon different configuration status of each first port configures each retry buffer. When a specific first port is configured on “merge” status, the buffer-configuration subunit can follows up to configure the retry buffer owned by the specific first port and the retry buffers owned but disused by the other first ports to constitute a buffer group with merging of storing spaces of said configured retry buffers.

Abstract: The present invention discloses reconfigurable data transmission ports with flow controlling unit in a computerized computer and the method for performing the same. When a specific first port is configured on “merge” status, a buffer-configuration subunit of the flow controlling unit can compliantly configure a receiving buffer owned by the specific first port and at least one receiving buffer owned but disused by the other first port to constitute a buffer group with merging of storing spaces of said configured receiving buffers. A credit message covering empty part of the merged storing space of the buffer group is reported from the specific first port to a credit tracker of a correspond second port thereby determining whether a data is send from the second port to be stored within the buffer group for data consumption of the specific first port from the buffer group.

Abstract: A method for PCI Express Power Management using a PCI PM mechanism in a computer system. The computer system includes a PCI PME (Power Management Event) controller and a PCI Express Root Complex. The method includes converting a Beacon signal generated by the PCI Express Root Complex into a Pseudo-PME signal, the Beacon signal asserting the Pseudo-PME signal. A Pseudo-PME line electrically connected with an PME input of the PCI PME controller and the PCI Express Root Complex is provided for transmitting the Pseudo-PME signal to the PCI PME controller. The PME input receives PME signals generated by PCI-compliant devices through a PCI Bus of the computer system. Before the computer system is under the control of an operating system, the Pseudo-PME signal is de-asserted.