Abstract: An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.

Abstract: An optical network unit (ONU) circuit that combines both analog and digital components is provided. The ONU circuit enhances the monitoring and diagnostic of the ONU optical interface, and thus improves the overall performance of the PON. Furthermore, the disclosed ONU circuit is integrated in a single chip and thus reduces the power consumption of an ONU system and the cost to manufacture.

Abstract: An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.

Abstract: A synchronization method including running (10) a system (725) having multiple agents (730) in parallel operation and forcing synchronization order (20, 30, 40, 50) between the multiple agents at at least one intervention juncture. Preferably, the multiple agents (730) include at least two agents (570, 590) accessing a single address at almost the same time. Further preferably, the forcing step includes forcing a predetermined one (570) of said two agents to access said address before the other one (590) of said two agents accesses said address.

Abstract: A synchronization method including running a system (725) having multiple agents (730 and 780) in parallel operation, the multiple agents each having at least one path (732) to a common bus (734). A bus arbitration mechanism (728) is used to synchronize between said multiple agents in accordance with a predetermined scheme, including blocking (310) at least one individual agent's path to the common bus (734) if said scheme indicates (315) that said individual agent is not to be activated, and restoring (320) said at least one individual agent's path (730) to the common bus (734) once said scheme indicates that said individual agent (730) can be activated.

Abstract: A method for the automatic verification of external interrupts in modern processor architectures under a very wide range of instruction sequences provides almost complete expected results from each of the involved interrupts. In particular, the method allows the verification of the architectural aspects to the external interrupt mechanism in pipelined and super scalar microprocessors. The method which is based on the assumption that when an external interrupt is serviced, the processor branches to a specific address according to the type of the external interrupt. The first step in the method is a preparation step wherein the memory addresses already used by the test are scanned and unused memory spaces are allocated for a plurality of memory blocks and two memory addresses for pointers. These two addresses are used to find the next block to fill. After this initial preparation step, the interrupt is presented in any desired location by the design simulator controller.

Abstract: In the dynamic process for the generation of biased pseudo-random test patterns for the functional verification of integrated circuit designs, the verification is performed in a sequence of steps, with each test pattern providing all data required to test a circuit design during at least one of said steps. Generation of each step is performed in two stages, where in a first stage all facilities and parameters required for the execution of the respective step are defined and assigned the proper values, and where in a second stage the execution of the particular step is performed. This process is continued until a test pattern with the number of steps requested by the user is generated, so that finally the test pattern comprises three parts: The initialized facilities define the initial machine state and execution parts of the test pattern, and the values of the facilities which have been changed during the execution of the steps, form the results part of the test pattern.