Abstract: A method to communicate data is disclosed which includes communicating a virtual address to a translation lookaside buffer (TLB) and translating the virtual address to a physical address of a computer memory. The method also includes loading the physical address translated by the TLB into a register within a processor and transmitting the data from the physical address to a destination computing device.

Abstract: Offloading data coherence operations from a primary processing unit(s) executing instantiated code responsible for data coherence in a shared-cache cluster to a data coherence offload engine reduces resource consumption and allows for efficient sharing of data in accordance with the data coherence protocol. Some of the data coherence operations, such as consulting and maintaining a directory, generating messages, and writing a data unit can be performed by a data coherence offload engine. The data coherence offload engine indicates availability of the data unit in the memory to the appropriate instantiated code. Hence, the instantiated code (the corresponding primary processing unit) is no longer burdened with some of the work load of data coherence operations. Migration of tasks from a primary processing unit(s) to data coherence offload engines allows for efficient retrieval and writing of a requested data unit.

Abstract: The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If there is a register dependency between a greater width producer instruction and a lesser width consumer instruction, a greater width source register is substituted for the source register specified by the lesser width producer. If there is a register dependency between a lesser width producer instruction and a greater width producer instruction, the greater width consumer instruction is replaced by multiple helper instructions. One or more of the helper instructions merge lesser width registers aliased onto the source registers specified by the greater width consumer instruction, into temporary registers. Another helper instruction executes the greater width consumer instruction using the temporary registers instead of the original source registers.

Abstract: The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Such instructions are treated as complex instructions. The functionality of a complex instruction is shared among multiple helpers so that by executing the helpers representing the complex instruction, the functionality of complex instruction is achieved. The expansion of complex instructions into helper instructions reduces the amount of hardware and complexity involved in supporting these individual complex instructions in various units in the processor.

Abstract: This document discusses, among other things, a system and method for connecting a plurality of memory controllers to one or more memory modules. Each memory module includes an advanced memory buffer (AMB) connected to a plurality of memory devices. A switch is connected between the plurality of memory controllers and the one or more memory modules. A memory read request is routed from one of the plurality of memory controllers through the switch to a preselected memory module.

Abstract: A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

Abstract: A method and apparatus to determine readiness of a complex instruction for retirement includes decoding a complex instruction into a plurality of helper instructions; executing the plurality of helper instructions using an execution unit; indicating the plurality of helper instructions that are alive using a live instruction register; and maintaining a complex instruction identification for the complex instruction using a complex instruction identification register.

Abstract: A method and apparatus for implementing vertical multi-threading in a microprocessor without implementing additional signal wires in the processor has been developed. The method uses a pre-existing signal to serve as a multi-function signal such that the multi-function signal can be used for clock enable, clock disable, and scan enable functions. The single multi-function signal exhibits multiple functionalities as needed by a flip-flop to operate in a plurality of modes. The method allows for the use of a pre-existing signal wire to be used as a process thread switch signal that would otherwise have to be explicitly hard-wired in the absence of the multi-functioning signal. The method further includes allowing multiple-bit flip-flops to be placed at sequential stages in a pipeline in order to facilitate vertical multi-threading and, in effect, increase processor performance. The apparatus provides means for distinguishing between specific characteristics exhibited by the multi-function signal.

Abstract: A technique for flattening architectural register windows into flattened space depending on a current window pointer to a register window is provided. The technique involves converting an n-bit value of a particular register in a register window to an x-bit value dependent on the current window pointer, where x is greater than n, and where the x-bit value is used for register dependency checking among a plurality of instructions.

Abstract: A technique for handling a condition code modifying instruction in an out-of-order multi-stranded processor involves providing a condition code architectural register file for each strand, providing a condition code working register file, and assigning condition code architectural register file identification information (CARF_ID) and condition code working register file identification information (CWRF_ID) to the condition code modifying instruction. CARF_ID is used to index a location in a condition code rename table to which the CWRF_ID is stored. Thereafter, upon an exception-free execution of the condition code modifying instruction, a result of the execution is copied from the condition code working register file to the condition code architectural register file dependent on CARF_ID, CWRF_ID, register type information, and strand identification information.

Abstract: A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill instructions without having to determine whether a remaining portion of the fill instructions will execute without exceptions.

Abstract: A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the spill instructions without having to determine whether a remaining portion of the spill instructions will execute without exceptions.

Abstract: A microprocessor cache configuration for reducing database cache misses and improving the processing speed, comprising a level-1 data cache, and a page prefetch cache. The page prefetch cache is adjacent the level-1 data cache. The page prefetch cache is configured to receive and store one or more database pages. Additionally, a page prefetch instruction provides the database pages to the page prefetch cache. The page prefetch instructions are generated by a compiler or by developer software.

Abstract: A method for increasing the processing speed of database instructions using a page prefetch cache. More particularly, the method is executed on a microprocessor and reduces database cache misses and improves the processing speed. The method comprises enabling a page prefetch cache with a database application, issuing one or more page prefetch instructions, and determining whether the particular database page is in the page prefetch cache.

Abstract: A technique for handling window-fill and/or window-spill operations that improves the performance of a processor over traditional techniques is presented. The window-fill and window-spill operations can be handled in hardware using helper instructions (helpers) prior to the generation of a trap (exception). Fetched instructions are examined prior to forwarding for execution to detect a potential register window boundary condition necessitating, for example, a window-fill or window-spill operation. Vectors are generated for a helper storage within the processor to retrieve helpers for resolving the condition. The helpers are forwarded for execution prior to the instruction that would cause the condition. In some embodiments, to improve the processing, individual helper storages are implemented for every condition. The use of helpers to resolve a register window boundary condition eliminates the generation of a trap and the use of trap handler code.

Abstract: The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Such instructions are treated as complex instructions. The functionality of a complex instruction is shared among multiple helpers so that by executing the helpers representing the complex instruction, the functionality of complex instruction is achieved. The expansion of complex instructions into helper instructions reduces the amount of hardware and complexity involved in supporting these individual complex instructions in various units in the processor.

Abstract: A method for limiting a number of register file read ports used to process a store instruction includes decoding the store instruction, where the decoding generates a decoded store instruction, identifying a store data register and source operand registers included in the decoded store instruction, and appending a set of attribute fields to the decoded store instruction. Further, dependent on a value of at least one of the attribute fields, source values corresponding to the source operand registers are read using the register file read ports at a time that the store instruction is issued, and a store data value corresponding to the store data register is read using one of the register file read ports at a time that the store instruction is committed.

Abstract: The present application describes a method and a system for facilitating the execution of helper sets corresponding to atomic complex instructions. The atomicity of complex instructions is maintained by emptying load and/or store queues and locking the addressed location. Complex atomic instructions are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Emptying the load and/or store queues before processing the helper load/store prevents any potential deadlock condition (or competition among other load/store) for corresponding memory locations and facilitates in maintaining atomicity of the complex instruction.

Abstract: The present application describes a method and a system for facilitating atomicity of complex instructions in processor execution of helper instruction. Atomic complex instructions are handled by stalling the fetching of instruction upon recognizing atomic instruction in a group of fetched instructions. Complex atomic instructions are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Stalling the fetching facilitates the execution and completion of corresponding helper instructions and maintains the atomicity of the complex instruction.

Abstract: A multi-issue microprocessor selectively assigns, with particular emphasis on an particular type of instruction, in a plurality of instructions to various pipelines. The microprocessor maintains counts of the number of instructions assigned to a first pipeline and a second pipeline. Depending on these counts, the processor assigns instructions of the particular type in the plurality of instructions to the first and second pipelines.