Patents by Inventor Rachel Layda Abinan

Rachel Layda Abinan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit package system with bonding in via
    Patent number: 9000579
    Abstract: An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: April 7, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Dario S. Filoteo, Jr., Emmanuel Espiritu, Rachel Layda Abinan
  • Integrated circuit packaging system with interconnects and method of manufacture thereof
    Patent number: 8802555
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle and a lead adjacent to the die paddle; mounting an integrated circuit, having a bond pad, over the die paddle; forming a bonding interconnect on the bond pad; attaching a circuit end of an internal interconnect to the bonding interconnect, the bonding interconnect between the circuit end and the bond pad; and connecting a lead end of the internal interconnect to the lead.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Rachel Layda Abinan
  • Integrated circuit package system with heatspreader
    Patent number: 8395254
    Abstract: An integrated circuit package system includes providing a substrate having an integrated circuit, attaching a heatspreader having a force control protrusion on the substrate, and forming an encapsulant over the heatspreader and the integrated circuit.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 12, 2013
    Assignee: STATS Chippac Ltd.
    Inventors: Emmanuel Espiritu, Dario S. Filoteo, Jr., Leo A. Merilo, Philip Lyndon Cablao, Rachel Layda Abinan, Allan Ilagan
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20120241931
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle and a lead adjacent to the die paddle; mounting an integrated circuit, having a bond pad, over the die paddle; forming a bonding interconnect on the bond pad; embedding a circuit end of an internal interconnect in the bonding interconnect; and connecting a lead end of the internal interconnect to the lead.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Rachel Layda Abinan
  • Integrated circuit package system having interconnect stack and external interconnect
    Patent number: 8138080
    Abstract: An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: March 20, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Dario S. Filoteo, Jr., Leo A. Merilo, Philip Lyndon Cablao, Emmanuel Espiritu, Rachel Layda Abinan, Allan Ilagan
  • Stacked integrated circuits package system with passive components
    Patent number: 8026129
    Abstract: A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive component between the second stack layer and the first stack layer.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: September 27, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Philip Lyndon Cablao, Dario S. Filoteo, Jr., Leo A. Merilo, Emmanuel Espiritu, Rachel Layda Abinan, Allan Ilagan
  • Integrated circuit packaging system with interposer
    Patent number: 7911046
    Abstract: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: March 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Philip Lyndon Cablao, Rachel Layda Abinan, Dario S. Filoteo, Jr., Allan P. Ilagan
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
    Publication number: 20090152704
    Abstract: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.
    Type: Application
    Filed: February 24, 2009
    Publication date: June 18, 2009
    Inventors: Philip Lyndon Cablao, Rachel Layda Abinan, Dario S. Filoteo, Jr., Allan P. Ilagan
  • Integrated circuit packaging system with interposer
    Patent number: 7518226
    Abstract: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: April 14, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Philip Lyndon Cablao, Rachel Layda Abinan, Dario S. Filoteo, Jr., Allan P. Ilagan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH BONDING IN VIA
    Publication number: 20080237873
    Abstract: An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening in the substrate open at the top and having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Il Kwon Shim, Dario S. Filoteo, Emmanuel Espiritu, Rachel Layda Abinan
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
    Publication number: 20080185719
    Abstract: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 7, 2008
    Inventors: Philip Lyndon Cablao, Rachel Layda Abinan, Dario S. Filoteo, Allan P. Ilagan