Abstract: An example apparatus comprises a first compute node including a first processor; a second compute node including a second processor; an input/manta (I/O) interface to selectively couple the first and second compute nodes to a set of I/O resources; and a voltage regulator including a set of power phase circuits, the voltage regulator to operate in a fault tolerant mode to provide power from selected ones of a first portion of the set of power phase circuits to the first compute node and to provide power from selected ones of a second portion of the set of power phase circuits to the second compute node.

Abstract: An example apparatus comprises a first compute node including a first processor; a second compute node including a second processor; an input/manta (I/O) interface to selectively couple the first and second compute nodes to a set of I/O resources; and a voltage regulator including a set of power phase circuits, the voltage regulator to operate in a fault tolerant mode to provide power from selected ones of a first portion of the set of power phase circuits to the first compute node and to provide power from selected ones of a second portion of the set of power phase circuits to the second compute node.

Abstract: Examples disclose a multi-core circuit with a primary core associated with a primary portion of cache and a secondary core associated with a secondary portion of the cache. The secondary portion of the cache is redundant to the primary portion of the cache. Further, the examples of the multi-core circuit provide a control circuit to enable the secondary core for operation in response to a fault condition detected at the primary core, wherein the secondary portion of cache is enabled with the secondary core to resume an operation of the primary core.

Abstract: A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

Abstract: An electronic device includes a housing defining an enclosure, one or more processors in the enclosure, and one or more memory modules in the enclosure. Disk storage drives are provided in an in-line arrangement within the enclosure such that a rear portion of one disk storage drive is adjacent a front portion of another disk storage drive.

Abstract: A computer power management system (10) can include power demand logic (20) of a computer component (12) that can generate a power demand signal corresponding to a predicted power demand determined for the computer component (12). A voltage regulator down (VRD) system (14) includes at least one power phase (18). The VRD system (14) can selectively adjust an input power to the computer component (12) based on power efficiency in response to the power demand signal.

Abstract: A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

Abstract: An electronic device includes a housing defining an enclosure, one or more processors in the enclosure, and one or more memory modules in the enclosure. Disk storage drives are provided in an in-line arrangement within the enclosure such that a rear portion of one disk storage drive is adjacent a front portion of another disk storage drive.

Abstract: A finite state electrical automaton modeled after a human neuron comprises a plurality of weighted inputs that pass into a state computing unit. A feedback mechanism changes the weights of the inputs as needed to control the response of the automaton to a desired output. A clock signal allows the automaton to function as a discrete time system. Unlike the threshold gates, the present automaton is capable of outputting an n-bit digital value analogous to a cell membrane potential. Because this automaton is capable of outputting more than two simple states it is a better building block for building neural nets.

Abstract: A finite state electrical automaton modeled after a human neuron comprises a plurality of weighted inputs that pass into a state computing unit. A feedback mechanism changes the weights of the inputs as needed to control the response of the automaton to a desired output. A clock signal allows the automaton to function as a discrete time system. Unlike the threshold gates, the present automaton is capable of outputting an n-bit digital value analogous to a cell membrane potential. Because this automaton is capable of outputting more than two simple states it is a better building block for building neural nets.