Patents by Inventor Radhakrishnan Nair
Radhakrishnan Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240161884Abstract: Systems and techniques are described herein for user identification. For instance, a technique can include receiving at least one biosignal from a sensor, the at least one biosignal indicative of a blood perfusion of a user. The technique can further include extracting at least one feature from the at least one biosignal, comparing the extracted at least one feature to at least one template feature associated with an enrolled user, determining, based on comparing the extracted at least one feature to the at least one template feature, whether the user matches the enrolled user, and outputting an indication of whether the user matches the enrolled user.Type: ApplicationFiled: November 14, 2022Publication date: May 16, 2024Inventors: Emily Kathryn BROOKS, Collin D'SOUZA, John Keith SCHNEIDER, Alexei STOIANOV, Shounak Uday GORE, Rathin RADHAKRISHNAN NAIR
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Publication number: 20220294231Abstract: The invention concerns a method for controlling a hybrid power generation plant comprising a plurality of power sources among a hydro plant, a solar plant and a battery storage system, said method comprising: receiving from a grid to which the plant is connected at least one data among a power demand, a peak hour, a frequency, a ramp, a reactive power, a voltage; varying a power production of at least one of the plurality of power sources, depending on said at least one data received from the grid and at least one characteristic of each of said plurality of power sources.Type: ApplicationFiled: March 10, 2022Publication date: September 15, 2022Inventors: Veena PADMARAO, Raganathan RADHAKRISHNAN NAIR, Arvind Kumar TIWARI, Santhosh Kumar C, José Luis FERRAL
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Patent number: 9406346Abstract: An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.Type: GrantFiled: September 28, 2011Date of Patent: August 2, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
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Patent number: 9218852Abstract: An apparatus includes a first semiconductor device including a memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device includes a second serializer/deserializer communication interface coupled to a first serializer/deserializer communication interface of a memory controller.Type: GrantFiled: September 28, 2011Date of Patent: December 22, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
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Patent number: 9180271Abstract: A respiratory therapy device has both a standard positive expiratory pressure (PEP) device and an oscillatory PEP device packaged together. A manually operable member is movable to select which of the standard and oscillatory PEP device is placed in communication with a patient's airway. A nebulizer connector may also be provided for connection of a nebulizer.Type: GrantFiled: March 5, 2012Date of Patent: November 10, 2015Assignee: Hill-Rom Services Pte. Ltd.Inventors: Mike Yang Chang Guo, Soo Yao Jee, Radhakrishnan Nair Oravielil Kamalashi
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Patent number: 9177609Abstract: An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.Type: GrantFiled: September 28, 2011Date of Patent: November 3, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
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Patent number: 9177612Abstract: An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.Type: GrantFiled: April 7, 2014Date of Patent: November 3, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
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Patent number: 9177610Abstract: An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.Type: GrantFiled: April 7, 2014Date of Patent: November 3, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
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Patent number: 9177611Abstract: An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The apparatus includes a second semiconductor device coupled to the first semiconductor device. The second semiconductor device includes a charge pump, and the 3D memory does not include a charge pump.Type: GrantFiled: April 7, 2014Date of Patent: November 3, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
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Patent number: 9142261Abstract: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.Type: GrantFiled: April 7, 2014Date of Patent: September 22, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
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Patent number: 8862967Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.Type: GrantFiled: April 19, 2012Date of Patent: October 14, 2014Assignee: Sandisk Technologies Inc.Inventors: Deepak Pancholi, Manuel Antonio D'Abreu, Radhakrishnan Nair, Stephen Skala
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Publication number: 20140218997Abstract: An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: MANUEL ANTONIO D'ABREU, STEPHEN SKALA, DIMITRIS PANTELAKIS, RADHAKRISHNAN NAIR, DEEPAK PANCHOLI
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Publication number: 20140218996Abstract: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: MANUEL ANTONIO D'ABREU, STEPHEN SKALA, DIMITRIS PANTELAKIS, RADHAKRISHNAN NAIR, DEEPAK PANCHOLI
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Publication number: 20140219031Abstract: An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The apparatus includes a second semiconductor device coupled to the first semiconductor device. The second semiconductor device includes a charge pump, and the 3D memory does not include a charge pump.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: MANUEL ANTONIO D'ABREU, STEPHEN SKALA, DIMITRIS PANTELAKIS, RADHAKRISHNAN NAIR, DEEPAK PANCHOLI
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Publication number: 20140219022Abstract: An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: MANUEL ANTONIO D'ABREU, STEPHEN SKALA, DIMITRIS PANTELAKIS, RADHAKRISHNAN NAIR, DEEPAK PANCHOLI
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Publication number: 20130246878Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.Type: ApplicationFiled: April 19, 2012Publication date: September 19, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: DEEPAK PANCHOLI, MANUEL ANTONIO D'ABREU, RADHAKRISHNAN NAIR, STEPHEN SKALA
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Publication number: 20130228174Abstract: A respiratory therapy device has both a standard positive expiratory pressure (PEP) device and an oscillatory PEP device packaged together. A manually operable member is movable to select which of the standard and oscillatory PEP device is placed in communication with a patient's airway. A nebulizer connector may also be provided for connection of a nebulizer.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Inventors: Mike Yang Chang Guo, Soo Yao Jee, Radhakrishnan Nair Oravielil Kamalashi
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Publication number: 20130003480Abstract: An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.Type: ApplicationFiled: September 28, 2011Publication date: January 3, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: MANUEL ANTONIO D'ABREU, STEPHEN SKALA, DIMITRIS PANTELAKIS, RADHAKRISHNAN NAIR, DEEPAK PANCHOLI
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Publication number: 20130007349Abstract: An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.Type: ApplicationFiled: September 28, 2011Publication date: January 3, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: MANUEL ANTONIO D'ABREU, STEPHEN SKALA, DIMITRIS PANTELAKIS, RADHAKRISHNAN NAIR, DEEPAK PANCHOLI
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Publication number: 20130007350Abstract: An apparatus includes a first semiconductor device including a memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device includes a second serializer/deserializer communication interface coupled to a first serializer/deserializer communication interface of a memory controller.Type: ApplicationFiled: September 28, 2011Publication date: January 3, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: MANUEL ANTONIO D'ABREU, STEPHEN SKALA, DIMITRIS PANTELAKIS, RADHAKRISHNAN NAIR, DEEPAK PANCHOLI