Abstract: A fault tolerant memory and method for sensing is disclosed. A pair of memory cells each including a memory device and a select device are connected to a pair of bit lines. The bit lines are connected through select devices to a differential sense amplifier. Each pair of memory cells stores a single bit of data; the first memory cell stores the data bit and the second memory cell stores the compliment of the data bit. The memory cells are fabricated such that they exhibit three states; a first state in which they conduct current, a second state in which they do not conduct current, and a third, abnormal, state into which they fail wherein they conduct approximately half of the current which would be conducted in the first state.