Abstract: In any of the post-global physical design phases an integrated circuit chip is wired in parallel. The chip is first divided into adjacent bays with rough wiring coordinates from the global wiring phase. Next the bays are grouped into bay groups, with each bay group containing a contiguous group of non-edge bays as well as edge bays which are adjacent another bay group. Each bay group is assigned to a wiring task on a processor, so that the wiring of the bay groups is performed in parallel, using the rough coordinates from the global wiring phase. The wiring tasks are coordinated regarding edge bays in order to achieve wiring consistency between bay groups.

Abstract: A method for allowing multiple users to simultaneously edit circuit wiring data, such as VLSI circuit data. The circuit data, contained in a computer database, is partitioned into a plurality of "parcels". Two types of wiring networks are identified within each parcel, internal and external. An internal network is completely enclosed within a parcel, whereas an external net spans two or more parcels. Each of the parcels may be simultaneously worked on by an individual user or circuit designer. Changes made to an internal wiring network has no impact on any of the other parcels. Changes made to an external wiring network does impact on other parcels which share the external network. A "design controller" is provided which restricts editing accessibility of an external network to one user at a time and locks out all other users. After changes are made to an external wiring network the database and the other parcels are updated to reflect the changes before the external network can be accessed again.