Patents by Inventor RAGHAVAN KUMAR
RAGHAVAN KUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10860682Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.Type: GrantFiled: April 2, 2020Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Phil Knag, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Abhishek Sharma, Sasikanth Manipatruni, Amrita Mathuriya, Ram Krishnamurthy, Ian A. Young
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Patent number: 10831446Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit×n-bit multiplications.Type: GrantFiled: September 28, 2018Date of Patent: November 10, 2020Assignee: Intel CorporationInventors: Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil Knag, Ram Krishnamurthy, Sasikanth Manipatruni, Amrita Mathuriya, Abhishek Sharma, Ian A. Young
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Patent number: 10825511Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.Type: GrantFiled: May 20, 2019Date of Patent: November 3, 2020Assignee: Intel CorporationInventors: Vivek De, Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Raghavan Kumar
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Patent number: 10825509Abstract: A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.Type: GrantFiled: September 28, 2018Date of Patent: November 3, 2020Assignee: Intel CorporationInventors: Huseyin Ekin Sumbul, Gregory K. Chen, Raghavan Kumar, Phil Knag, Abhishek Sharma, Sasikanth Manipatruni, Amrita Mathuriya, Ram Krishnamurthy, Ian A. Young
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Publication number: 20200334161Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution.Type: ApplicationFiled: July 6, 2020Publication date: October 22, 2020Applicant: Intel CorporationInventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor Lee, Huseyin Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, IAN YOUNG, Abhishek Sharma
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Publication number: 20200312404Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.Type: ApplicationFiled: May 20, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Vivek De, Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Raghavan Kumar
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Patent number: 10754619Abstract: An embodiment of a semiconductor package apparatus may include technology to provide an entropy extractor including a physically unclonable function (PUF), a true random number generator (TRNG), an entropy source coupled to both the PUF and the TRNG, and a circuit to self-calibrate the entropy extractor. Other embodiments are disclosed and claimed.Type: GrantFiled: September 27, 2018Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Sudhir Satpathy, Sanu Mathew, Vikram Suresh, Raghavan Kumar
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Patent number: 10748603Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.Type: GrantFiled: September 28, 2018Date of Patent: August 18, 2020Assignee: Intel CorporationInventors: Huseyin Ekin Sumbul, Gregory K. Chen, Raghavan Kumar, Phil Knag, Abhishek Sharma, Sasikanth Manipatruni, Amrita Mathuriya, Ram Krishnamurthy, Ian A. Young
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Publication number: 20200233923Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.Type: ApplicationFiled: April 2, 2020Publication date: July 23, 2020Inventors: Phil KNAG, Gregory K. CHEN, Raghavan KUMAR, Huseyin Ekin SUMBUL, Abhishek SHARMA, Sasikanth MANIPATRUNI, Amrita MATHURIYA, Ram KRISHNAMURTHY, Ian A. YOUNG
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Patent number: 10713558Abstract: In one embodiment, a method comprises determining that a membrane potential of a first neuron of a first neuron core exceeds a threshold; determining a first plurality of synapse cores that each store at least one synapse weight associated with the first neuron; and sending a spike message to the determined first plurality of synapse cores.Type: GrantFiled: December 30, 2016Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Huseyin Ekin Sumbul, Gregory K. Chen, Raghavan Kumar, Phil Knag, Ram K. Krishnamurthy
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Patent number: 10705967Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution.Type: GrantFiled: October 15, 2018Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor Lee, Huseyin Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young, Abhishek Sharma
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Patent number: 10642922Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.Type: GrantFiled: September 28, 2018Date of Patent: May 5, 2020Assignee: Intel CorporationInventors: Phil Knag, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Abhishek Sharma, Sasikanth Manipatruni, Amrita Mathuriya, Ram Krishnamurthy, Ian A. Young
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Publication number: 20200135266Abstract: A loaded capacitance static random-access memory (C-SRAM) is provided. The C-SRAM is configured to prevent full bit line discharge during a functional reads even where the number of bit cells on the bit lines is small. The C-SRAM includes one or more loaded capacitance structures that may take any of a variety of physical configurations designed to provide additional capacitance to the bit lines. For instance, the loaded capacitance structures may take the form of a MIM capacitor in which a ferroelectric layer is formed from one or more high K materials. In addition, the loaded capacitance structures may be positioned in a variety of locations within the C-SRAM, including the back end of line.Type: ApplicationFiled: October 30, 2018Publication date: April 30, 2020Applicant: INTEL CORPORATIONInventors: Raghavan Kumar, Sasikanth Manipatruni, Gregory Chen, Huseyin Ekin Sumbul, Phil Knag, Ram Krishnamurthy, Ian Young, Mark Bohr, Amrita Mathuriya
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Patent number: 10635404Abstract: In one embodiment, an apparatus comprises a multiplier circuit to: identify a point multiply operation to be performed by the multiplier circuit, wherein the point multiply operation comprises point multiplication of a first plurality of operands; identify a point add operation associated with the point multiply operation, wherein the point add operation comprises point addition of a second plurality of operands, wherein the second plurality of operands comprises a first point and a second point, and wherein the first point and the second point are associated with a first coordinate system; convert the second point from the first coordinate system to a second coordinate system; perform the point add operation based on the first point associated with the first coordinate system and the second point associated with the second coordinate system; and perform the point multiply operation based on a result of the point add operation.Type: GrantFiled: June 29, 2017Date of Patent: April 28, 2020Assignee: Intel CorporationInventors: Sudhir K. Satpathy, Raghavan Kumar, Arvind Singh, Vikram B. Suresh, Sanu K. Mathew
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Publication number: 20200105833Abstract: A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Jack T. KAVALIEROS, Ian A. YOUNG, Ram KRISHNAMURTHY, Ravi PILLARISETTY, Sasikanth MANIPATRUNI, Gregory CHEN, Hui Jae YOO, Van H. LE, Abhishek SHARMA, Raghavan KUMAR, Huichu LIU, Phil KNAG, Huseyin SUMBUL
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Publication number: 20200105337Abstract: Embodiments herein describe techniques for a semiconductor device including a memory cell. The memory cell includes a storage cell and a capacitor having a first electrode and a second electrode. The first electrode and the second electrode may be placed in a metal layer below a metal electrode coupled to one or more transistors of the storage cell. The storage cell is to store a digital value, where a voltage value of an output line of the storage cell is to be determined based on the digital value stored in the storage cell. The second electrode of the capacitor is coupled to the output line of the storage cell. The capacitor is to store a charge based on the voltage value of the output line of the storage cell. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Gregory CHEN, Raghavan KUMAR, Huseyin Ekin SUMBUL, Phil KNAG, Ram KRISHNAMURTHY, Sasikanth MANIPATRUNI, Amrita MATHURIYA, Abhishek SHARMA, Ian A. YOUNG
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Publication number: 20200104101Abstract: An embodiment of a semiconductor package apparatus may include technology to provide an entropy extractor including a physically unclonable function (PUF), a true random number generator (TRNG), an entropy source coupled to both the PUF and the TRNG, and a circuit to self-calibrate the entropy extractor. Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 27, 2018Publication date: April 2, 2020Applicant: Intel CorporationInventors: Sudhir Satpathy, Sanu Mathew, Vikram Suresh, Raghavan Kumar
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Publication number: 20200098826Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: Abhishek SHARMA, Gregory CHEN, Phil KNAG, Ram KRISHNAMURTHY, Raghavan KUMAR, Sasikanth MANIPATRUNI, Amrita MATHURIYA, Huseyin SUMBUL, Ian A. YOUNG
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Publication number: 20200097807Abstract: A compute near memory binary neural network accelerator with digital circuits that achieves energy efficiencies comparable to or surpassing a compute near memory binary neural network accelerator with analog circuits is provided. The compute near memory binary neural network accelerator with digital circuits is more process scalable, robust to process, voltage and temperature variations, and immune to circuit noise.Type: ApplicationFiled: November 27, 2019Publication date: March 26, 2020Inventors: Phil KNAG, Gregory K. CHEN, Raghavan KUMAR, Huseyin Ekin SUMBUL, Ram KRISHNAMURTHY
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Publication number: 20200098824Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a substrate, a RRAM storage cell above the substrate, and a diode adjacent to the RRAM storage cell. The RRAM storage cell includes a first electrode located in a first metal layer above the substrate, a resistive switching material layer adjacent to the first electrode, and a second electrode adjacent to the resistive switching material layer. The second electrode is shared between the RRAM storage cell and the diode. The diode includes the second electrode shared with the RRAM storage cell, a semiconductor layer adjacent to the second electrode, and a third electrode located in a second metal layer above the substrate. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Abhishek SHARMA, Gregory K. CHEN, Ram KRISHNAMURTHY, Ravi PILLARISETTY, Sasikanth MANIPATRUNI, Amrita MATHURIYA, Raghavan KUMAR, Phil KNAG, Huseyin SUMBUL, Urusa ALAAN, Noriyuki SATO