Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings extending through the alternating stack, and memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective memory film. Each of the electrically conductive layers includes a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures, an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers, and a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers. The memory opening fill structures are formed after performing a halogen outgassing anneal through the memory openings to reduce or eliminate the halogen outgassing damage in the layers of the memory film.

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers. The discrete ferroelectric material portions protrude inward into the memory opening relative to vertical sidewalls of the insulating layers.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and having a lateral undulation in a vertical cross-sectional profile such that the memory opening laterally protrudes outward at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and including a vertical stack of blocking dielectric material portions located at the levels of the electrically conductive layers, a vertical stack of discrete memory elements located at the levels of the electrically conductive layers and including a respective contoured charge storage material portion, a tunneling dielectric layer overlying the contoured inner sidewalls of the tubular charge storage material portion, and a vertical semiconductor channel.

Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

Abstract: A first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers is formed over a substrate. A first-tier memory opening is formed, and is filled with a first-tier sacrificial memory opening fill structure. A second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers is formed. An etch mask layer is formed, and a second-tier memory opening is formed through the second-tier alternating stack. An etch mask removal process is performed which collaterally removes a top portion of the first-tier sacrificial memory opening fill structure. A sacrificial pillar structure is formed by performing a selective material deposition process. An inter-tier memory opening is formed by removing the first-tier sacrificial memory opening fill structure and at least a central portion of the sacrificial pillar structure.

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and composite layers that are interlaced along a vertical direction, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and an inner ferroelectric material layer including a first ferroelectric material, and a vertical stack of electrically-non-insulating material portions located between the inner ferroelectric material layer and the composite layers. Each of the composite layers includes a respective electrically conductive layer and a respective outer ferroelectric material layer including a second ferroelectric material, embedding the respective electrically conductive layer, and contacting a respective electrically-non-insulating material portion.

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Abstract: At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each of the electrically conductive layers include a molybdenum layer and a plurality of conductive capping material portions in contact with an outer sidewall of a respective one of the memory opening fill structures.

Abstract: A three dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory stack structures vertically extending through the alternating stack; and a backside trench fill structure. The backside trench fill structure includes a backside trench insulating spacer and a backside contact via structure. The backside contact via structure may include a tapered metallic nitride liner and at least one core fill conductive material portion. Alternatively, the backside contact via structure may include a tungsten nitride liner, a metallic nitride liner other than tungsten nitride, and at least one core fill conductive material portion.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a first backside trench fill structure and a second backside trench fill structure. Each of the electrically conductive layers includes a respective metal nitride liner and a respective metal fill material region. The respective metal fill material region includes a respective first-thickness portion having a respective first vertical thickness and a respective second-thickness portion having a respective second vertical thickness that is greater than the respective first vertical thickness.

Abstract: A structure includes semiconductor devices located over a substrate, a first interconnect-level dielectric layer located above the semiconductor devices, a first metal structure embedded in the first interconnect-level dielectric layer, where a top surface of the first metal structure and a top surface of the first interconnect-level dielectric layer are located in a same first horizontal plane, a spacer dielectric material layer having a contoured top surface and a planar bottom surface located in the first horizontal plane on the top surface of the first interconnect-level dielectric layer, at least one opening located in the spacer dielectric material layer, a metal cap structure located in the at least one opening and having a bottom surface in contact with at least a portion of the top surface of the first metal structure, and a second metal structure located on a top surface of the metal cap structure.

Abstract: A method of forming a memory device includes forming an alternating stack of disposable material layers and silicon nitride layers over a substrate, forming a memory opening through the alternating stack, forming a memory film in the memory opening, forming a vertical semiconductor channel over the memory film in the memory opening, forming a backside trench through the alternating stack, forming laterally-extending cavities by removing the disposable material layers selective to the silicon nitride layers through the backside trench, oxidizing portions of the silicon nitride layers exposed in the laterally-extending cavities to form insulating layers, and replacing remaining portions of the silicon nitride layers with electrically conductive layers.

Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate; forming an etch mask material layer containing an opening over the alternating stack; performing a first anisotropic etch process that etches unmasked upper portions of the alternating stack to form a via opening below the opening in the etch mask material layer; forming a combination of a non-conformal cladding liner and a conformal sacrificial spacer layer over the etch mask material layer and in peripheral portions of the via opening; performing a punch-through process that etches a horizontally-extending portion of the conformal sacrificial spacer layer from a bottom portion of the via opening; and vertically extending the via opening by performing a second anisotropic etch process that etches unmasked lower portions of the alternating stack selective to the non-conformal cladding liner and the conformal sacrificial spacer layer.