Abstract: Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs include a vector processing stage(s) configured to process vector data according to a vector instruction executed in the vector processing stage. Each vector processing stage includes vector processing blocks each configured to process vector data based on the vector instruction being executed. The vector processing blocks are capable of providing different vector operations for different types of vector instructions based on data path configurations. Data paths of the vector processing blocks are programmable to be reprogrammable to process vector data differently according to the particular vector instruction being executed.

Abstract: The present invention relates generally to cosmetic powder compositions for topical application to a keratinous surface, as well as to the delivery of cosmetic actives using the cosmetic powder compositions. In particular, the cosmetic powder compositions of the present invention comprise actives for delivery to the skin, such actives providing aesthetic and therapeutic benefits to the skin, such as, by improving the condition and appearance of skin affected by signs of chronological, hormonal, or photo-aging.

Abstract: Systems and method for reading data samples in reverse group order are described herein according to various embodiments of the present disclosure. In one embodiment, a method for reading data samples in a memory is provided, wherein the data samples correspond to an operand of a vector operation, the data samples are grouped into a plurality of different groups, and the different groups are spaced apart by a plurality of addresses in the memory. The method comprises reading the groups of data samples in reverse group order, and, for each group, reading the data samples in the group in forward order.

Abstract: Systems and methods for despreading a received signal are described herein. In one embodiment, a vector processor comprises a plurality of code generators, wherein each code generator is configured to generate a different code corresponding to a different code hypothesis. The vector processor also comprises a plurality of despread blocks coupled to a common input for receiving samples of a signal, wherein each despread block is configured to despread at least a portion of the samples with a different one of the codes to generate respective despreaded samples and to accumulate the respective despreaded samples over a length of the code.

Abstract: A method of manufacturing a cosmetic applicator formed of a substrate and an application element comprising one or more application areas that are cohesively maintained on the substrate in a gapless, side-by-side formation in the presence of wet and/or dry binders. The substrate is subjected to a wetting agent that provides a better bind for the cosmetic slurries as they are printed onto their respective application area. The cosmetic compositions of each cosmetic application area may be different. Various cosmetic effects may be provided to end-users in a portable application.

Abstract: Vector processing engines (VPEs) having programmable data path configurations for providing multi-mode Radix-2X butterfly vector processing circuits. Related vector processors, systems, and methods are also disclosed. The VPEs disclosed herein include a plurality of vector processing stages each having vector processing blocks that have programmable data path configurations for performing Radix-2X butterfly vector operations to perform Fast Fourier Transform (FFT) vector processing operations efficiently. The data path configurations of the vector processing blocks can be programmed to provide different types of Radix-2X butterfly vector operations as well as other arithmetic logic vector operations.

Abstract: Systems and methods for performing a rake-finger operation on a vector processor are described herein. In one embodiment, a method for rake-finger processing comprises loading samples from a register into an execution unit, performing a rake-finger operation on the samples in the execution unit, and writing results from the rake-finger operation to the register. Performing the rake-finger operation comprises performing a finite impulse response (FIR) filter operation, and performing a despread operation, wherein filtered samples from the FIR filter operation are input to the despread operation without going through the register.

Abstract: Systems and methods for generating twiddle factors are described herein according to various embodiments of the present disclosure. In one embodiment, a method for twiddle factor generation comprises generating a first twiddle phase, wherein the first twiddle phase is from a set of radix-M1 twiddle phases, and M1 is an integer. The method also comprises converting the first twiddle phase into a second twiddle phase, wherein the second twiddle phase is from a set of radix-M2 twiddle phases, and M2 is an integer that is different from M1. The method further comprises generating a twiddle factor based on the second twiddle phase.

Abstract: A cosmetic applicator and method of manufacturing same, wherein the cosmetic applicator is formed of a substrate and an application element comprising one or more application areas that are cohesively maintained on the substrate in a gapless, side-by-side formation in the presence of wet and/or dry binders. The substrate is subjected to a wetting agent that provides a better bind for the cosmetic slurries as they are printed onto their respective application area. The cosmetic compositions of each cosmetic application area may be different. Various cosmetic effects may be provided to end-users in a portable application.

Abstract: Techniques for fast power gating of vector processors are described herein. In one embodiment, a method for power gating a vector processor comprises powering up a vector unit from an inactive state at approximately a boundary of a transmission time interval, and powering down the vector unit within the transmission time interval after the vector unit completes a task within the transmission time interval.

Abstract: Systems and methods for performing a rake-finger operation on a vector processor are described herein. In one embodiment, a method for rake-finger processing comprises loading samples from a register into an execution unit, performing a rake-finger operation on the samples in the execution unit, and writing results from the rake-finger operation to the register. Performing the rake-finger operation comprises performing a finite impulse response (FIR) filter operation, and performing a despread operation, wherein filtered samples from the FIR filter operation are input to the despread operation without going through the register.

Abstract: Systems and methods for despreading a received signal are described herein. In one embodiment, a vector processor comprises a plurality of code generators, wherein each code generator is configured to generate a different code corresponding to a different code hypothesis. The vector processor also comprises a plurality of despread blocks coupled to a common input for receiving samples of a signal, wherein each despread block is configured to despread at least a portion of the samples with a different one of the codes to generate respective despreaded samples and to accumulate the respective despreaded samples over a length of the code.

Abstract: Systems and methods for performing on-the-fly format conversion on data vectors during load/store operations are described herein. In one embodiment, a method for loading a data vector from a memory into a vector unit comprises reading a plurality of samples from the memory, wherein the plurality of samples are packed in the memory. The method also comprises unpacking the samples to obtain a plurality of unpacked samples, performing format conversion on the unpacked samples in parallel, and sending at least a portion of the format-converted samples to the vector unit.

Abstract: Systems and method for reading data samples in reverse group order are described herein according to various embodiments of the present disclosure. In one embodiment, a method for reading data samples in a memory is provided, wherein the data samples correspond to an operand of a vector operation, the data samples are grouped into a plurality of different groups, and the different groups are spaced apart by a plurality of addresses in the memory. The method comprises reading the groups of data samples in reverse group order, and, for each group, reading the data samples in the group in forward order.

Abstract: Methods for preparing a solid powder cosmetic composition comprise heating a wax component and one or more cosmetic powders at a temperature sufficient to melt the wax, and subsequently cooling the mixture to provide a solid composition comprising a wax matrix having particulate materials homogenously dispersed therein.

Abstract: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The merging circuitry is configured to merge an output vector data sample set from execution units as a result of performing vector processing operations in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory to be stored. The merged output vector data sample set is stored in a merged form in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in execution units.

Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption are disclosed. Related vector processor systems and methods are also disclosed. The VPEs are configured to provide filter vector processing operations. To minimize re-fetching of input vector data samples from memory to reduce power consumption, a tapped-delay line(s) is included in the data flow paths between a vector data file and execution units in the VPE. The tapped-delay line(s) is configured to receive and provide input vector data sample sets to execution units for performing filter vector processing operations. The tapped-delay line(s) is also configured to shift the input vector data sample set for filter delay taps and provide the shifted input vector data sample set to execution units, so the shifted input vector data sample set does not have to be re-fetched during filter vector processing operations.

Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision correlation/covariance vector processing operations with reduced sample re-fetching and/or power consumption are disclosed. The VPEs disclosed herein are configured to provide correlation/covariance vector processing operations, such as code division multiple access (CDMA) correlation/covariance vector processing operations as a non-limiting example. A tapped-delay line(s) is included in the data flow paths between memory and execution units in the VPE. The tapped-delay line (s) is configured to receive and provide an input vector data sample set to execution units for performing correlation/covariance vector processing operations.

Abstract: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The merging circuitry is configured to merge an output vector data sample set from execution units as a result of performing vector processing operations in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory to be stored. The merged output vector data sample set is stored in a merged form in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in execution units.

Abstract: Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided in data flow paths between vector data memory and execution units in the VPE. The format conversion circuitry is configured to convert input vector data sample sets fetched from vector data memory in-flight while the input vector data sample sets are being provided over the data flow paths to the execution units to be processed. In this manner, format conversion of the input vector data sample sets does not require pre-processing, storage, and re-fetching from vector data memory, thereby reducing power consumption and not limiting efficiency of the data flow paths by format conversion pre-processing delays.