Abstract: Systems and methods for monitoring impulse noise are described. At least one embodiment is a method, which comprises detecting whether impulse noise is present and in response to detecting the presence of impulse noise, performing time domain analysis to determine whether one or more impulse noise sources are present based on minimum interarrival time and maximum impulse length. The method further includes performing frequency domain analysis to estimate frequencies associated with the one or more impulse noise sources and based on the time domain analysis and frequency domain analysis, providing a total number of impulse noise sources and frequencies associated with the impulse noise sources. In this regard, the embodiments described herein provide dual-speed monitoring of impulse noise in the form of short-term and long-term monitoring.

Abstract: A method for tuning performance of an operating system, the method comprising identifying all sources of operating system jitter; measuring the impact of each of the operating system jitter source; and tuning performance of the operating system, preferably by use of different approaches/techniques, which could include removing the sources of operating system jitter and/or delaying their execution and/or smoothening their execution over a longer period of time. Computer program code and systems are also provided.

Abstract: A method, system and computer program product for conducting an online auction of a plurality of heterogeneous items between a plurality of selling and potential purchasing parties. The method includes the steps of accepting an offer in respect of an item, accepting one or more subsequent offers that is/are preferable to a previously accepted offer, and rejecting the previously accepted offer. While the offer/s is/are binding on a party making the offer, acceptance of the offer/s is/are not binding on a party accepting the offer. Classes of “seller strategies”, for offering items to potential purchasing parties, and “buyer strategies”, to decide which offers to accept, are also disclosed. As a result of the interaction of the buyer and seller strategies, the auction mechanism converges to an allocation of items to buyers at particular prices and assists in discovering a free and fair competitive equilibrium price.

Abstract: The invention provides a method for conducting an auction of a plurality of heterogeneous items. The method comprises making, by offering parties, offers to potential accepting parties for the heterogeneous items. The making begins at a specified time with at least some of the potential accepting parties and at least some of the offering parties represented by software-based agents hosted on terminals connected via a communication network. Any acceptance by any accepting party of any offer from any offering party is binding on the offering party immediately, but is not binding on the accepting party until the auction closes. The method also comprises accepting, by an accepting party, a first offer from a first offering party for the heterogeneous item only if the first offer provides a surplus of at least a minimum surplus amount for the heterogeneous item.

Abstract: Systems and methods for reducing the peak-to-average power ratio (PAR) at the transmitter can reduce the dynamic range required in various analog components. PAR can be reduced by applying a time-domain compensation signal in the oversampled regime, using tones reserved for PAR reduction. A set of vectors corresponding to PAR tones is generated by processing out-of-phase symbols for each PAR tone to form a span matrix. The span matrix is used to find a best fit of a desired target signal to a time-domain compensation signal comprising only PAR tones.

Abstract: A decision feedback equalizer (DFE) has an inter symbol interference (ISI) loop and inter chip interference (ICI) loop. A buffer at the input of the DFE loop receives a (CCK based data rate) signal coming into the DFE, retains a predetermined number of chips from each incoming symbol and assists to meet timing requirements by chip management. An outgoing rate for the chips from the buffer may depend on the incoming rate and may be higher than the incoming rate by a known factor. A method of designing a configuration for the DFE takes into consideration the timing delay in the loops. The operation within the DFE loop is pipelined, and any latency due to the pipelining is handled at a CCK demodulator. A method for designing the DFE architecture and an article comprising a storage medium with instructions thereon for executing the method, are also disclosed.

Abstract: A method for designing a decision feedback equalizer (DFE) that handles packet based input data signals uses an inter symbol interference (ISI) removal loop and an inter chip interference (ICI) removal loop which is nested inside the ISI loop, for maximum interference removal and limited error propagation. The DFE may use a feed forward filter and a series connected chip-flow control buffer for receiving the input data signals. The DFE of the invention has application in 802.11 b PHY and 802.11 g PHY scenarios and any application involving a DFE with the need for minimum error propagation. Taught herein is a combined weighted DFE with erasure provision and interference removal in an optional two step mechanism. An article comprising a computer storage medium to execute the DFE design method is also disclosed.

Abstract: A method and system for compensating for the effect of phase drift in a data sampling clock during data transfer between sub-systems of an electronic device. The sub-systems of the electronic device transfer data frame by frame. Each frame includes multiple data windows. Each data window includes multiple data bits. The method includes sampling each of the one or more data bits of a data window at one or more early instances, a prompt instance, and one or more late instances. Further, the method includes calculating the phase-error value of the sampled data window, based on the data sampled. Furthermore, the method includes compensating for the effect of phase drift in the data sampling clock, based on the calculated phase error value.

Abstract: A method and system for managing communications between sub-systems of a communication device. The sub-systems include a Radio Frequency Integrated Circuit (RFIC) and a Baseband Integrated Circuit (BBIC). The BBIC includes a processing engine, a state machine module and an interface module. The method includes initializing a Digital Radio Frequency Third Generation (DigRF3G) interface between the RFIC and the BBIC. The processing engine is kept functionally inactive during the initialization process of the DigRF3G interface. Further, the method includes exchanging one or more packets between the RFIC and the BBIC.

Abstract: A system for receiving and handling a scrambled input data signal that includes a preamble with a start of frame delimiter (SFD) initiates an SFD search on the scrambled input data, thereby attempting to save an initialization period. The initialization period may be of the order of 7 uS, and its saving results in improved timeline management enabling antenna diversity and the possible use of high performance algorithms. The system may use two parallel paths for signal processing, each having an SFD detector and a descrambler. If the detected SFD is short, then the second path is disabled, and if it is long, then the first parallel path is disabled. Alternatively, the first path can be used for a finite period of time (for e.g., 40 symbols) and if the SFD is still not detected, the first path is disabled, and the system uses only the second path.

Abstract: A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.

Abstract: A method of determining a synchronous phase includes receiving a correlation sequence, and selecting one or more correlated signals from the correlation sequence. Then, when the number of selected correlated signals is odd, the synchronous phase corresponding to a central correlated signal is selected.

Abstract: A method, apparatus and computer program product are disclosed for incrementally checkpointing the state of a computer memory in the presence of at least one executing software application at periodic instants. A secure hash function is periodically applied to each partitioned contiguous block of memory to give a periodic block hash value. At each periodic instant, a block hash value for each block is compared with a respective preceding block hash value to determine if said memory block has changed according to whether said block hash values are different. Only changed memory blocks are stored in a checkpoint record. The memory block sizes are adapted at each periodic instant to split changed blocks into at least two parts and to merge only two non-changed contiguous blocks at a time.

Abstract: A method, apparatus and computer program product are disclosed for incrementally checkpointing the state of a computer memory in the presence of at least one executing software application at periodic instants. A secure hash function is periodically applied to each partitioned contiguous block of memory to give a periodic block hash value. At each periodic instant, a block hash value for each block is compared with a respective preceding block hash value to determine if said memory block has changed according to whether said block hash values are different. Only changed memory blocks are stored in a checkpoint record. The memory block sizes are adapted at each periodic instant to split changed blocks into at least two parts and to merge only two non-changed contiguous blocks at a time.

Abstract: An electronic coupon, an electronic commerce system, and a method for the honoring of electronic coupons utilizing computing equipment are disclosed. In the method, an issuing party issues an electronic coupon to a customer. The customer presents the coupon for redemption to a redemption party. The redemption party transmits the coupon to an authentication party for authentication. If authentic, the authentication party charges the redemption party a fee and passes that fee to the issuing party. The redemption party honors the coupon for the customer and seeking reimbursement of the fee from the issuing party. The electronic coupon has a plurality of data fields, including: a coupon identifier, x, a first one-way hash function field, f(x), and a secure signature field.

Abstract: A method and system generates, distributes, stores, redeems, validates and clears electronic manufacturer coupons and electronic store coupons. A coupon mint generates unforgable blank digital coupons. The promoter of the offer then writes the terms and conditions and other details of the offer, on blank coupons to customize these. These customized coupons are digitally signed by the promoter and distributed to potential customers. A customer may either present these coupons electronically for redemption to an online store, or print these coupons and present them to a conventional offline store. The store may check the authenticity of a coupon by verifying the digital signature and also verifying if the coupon has not been used earlier by contacting a verification center. The store collects all redeemed coupons and sends these to manufacturer for clearing. The verification center verifies that the coupon is authentic and has not already been used before.

Abstract: The use of software-based agents to act on behalf of human bidders for dynamic participation in multiple simultaneous online auctions is disclosed. The software-based agents may reside on computer systems or on any type of stationary or mobile terminal. On the basis of bidding-related information from a bidder, a software agent selects a plurality of auctions to place bids in. Upon being outbid, the agent determines whether to place an additional bid in a further auction. The agent can make such a determination on the basis of maximising profitability or surplus.

Abstract: The present invention relates to a computer implementable system and method for allocation and pricing of classified resources of a web server farm to customers by a resource center comprising means for providing different levels of service by dynamically allocating and pricing said resources based on customers' changing needs, and their willingness to pay.

Abstract: A decision feedback equalizer (DFE) has an inter symbol interference (ISI) loop and inter chip interference (ICI) loop. A buffer at the input of the DFE loop receives a (CCK based data rate) signal coming into the DFE, retains a predetermined number of chips from each incoming symbol and assists to meet timing requirements by chip management. An outgoing rate for the chips from the buffer may depend on the incoming rate and may be higher than the incoming rate by a known factor. A method of designing a configuration for the DFE takes into consideration the timing delay in the loops. The operation within the DFE loop is pipelined, and any latency due to the pipelining is handled at a CCK demodulator. A method for designing the DFE architecture and an article comprising a storage medium with instructions thereon for executing the method, are also disclosed.

Abstract: A method for designing a decision feedback equalizer (DFE) that handles packet based input data signals uses an inter symbol interference (ISI) removal loop and an inter chip interference (ICI) removal loop which is nested inside the ISI loop, for maximum interference removal and limited error propagation. The DFE may use a feed forward filter and a series connected chip-flow control buffer for receiving the input data signals. The DFE of the invention has application in 802.11 b PHY and 802.11 g PHY scenarios and any application involving a DFE with the need for minimum error propagation. Taught herein is a combined weighted DFE with erasure provision and interference removal in an optional two step mechanism. An article comprising a computer storage medium to execute the DFE design method is also disclosed.