Abstract: A frequency divider has two or more storage elements connected in a loop. One of the outputs of each storage element is connected to one of the inputs of another storage element. Each storage element provides at least one output signal having a period equal to the period of a reference input signal multiplied by the number of interconnected storage elements. The reference input signal may be, for example, a local oscillator (“LO”) signal. In the case where the reference input signal has a 50% duty cycle, the output signals will also have a 50% duty cycle. Furthermore, in the case where a total of three storage elements are connected in a loop, the outputs of two of the three storage elements can be combined to provide a signal having substantially no third order harmonics.

Abstract: A distributed active transformer on a semiconducting substrate is provided. The distributed active transformer includes an outer primary, a secondary disposed adjacent to the outer primary, and an inner primary disposed adjacent to the outer primary and the secondary. A plurality of first three terminal devices is coupled to the outer primary at a plurality of locations. A plurality of second three terminal devices coupled to the inner primary at a plurality of locations, and each second three terminal device is disposed opposite from and coupled to one of the plurality of first three terminal devices. A plurality of power control actuation circuits is also provided, where each power control actuation circuit is coupled to one of the first three terminal devices and the second three terminal devices.

Abstract: A receiver front end is provided with a low-noise amplifier (LNA), a linearity on demand (LOD) circuit, and a gain calibration device. The LOD circuit provides current to the LNA depending on linearity requirements. The gain calibration device monitors the amount of current provided by the LOD circuit to the LNA and provides signals to help compensate for variations in the LNA's gain due to the variations in the current supplied to the LNA by the LOD circuit. The compensation signals may be used to adjust the gain of a variable-gain amplifier, or may comprise compensation parameters usable by a digital signal processor, to compensate for the gain variations.

Abstract: A direct conversion receiver for receiving a first input signal and directly downconverting it to baseband frequencies. The receiver includes a frequency translator which is responsive to a phase-split input signal having 2n components, wherein n is an integer greater than 1. The phase-split signal has a period T which is about n times the period of the first input. The frequency translator alternates, at a rate of about 2n/T, between switching the first input signal to a first output, and switching the first signal to a second output. A preprocessor is available to improve the switching characteristics of the phase-split input signal.

Abstract: A method and apparatus are provided for generating first and second modulation signals from a local oscillator signal for quadrature subharmonic modulation of a quadrature amplitude modulated information signal. The method includes the steps of delaying the local oscillator signal in a plurality of incremental odd and even delay steps to form respective sets of odd and even modulator signals, said odd set of modulator signals together forming the first modulation signal and said even set forming the second modulation signal for quadrature subharmonic modulation of the quadrature amplitude modulated information signal and controlling a magnitude of the incremental delays based upon a predetermined phase offset between the local oscillator signal and a last delay step of the incremental delay steps.

Abstract: Systems for controlling the frequency of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system comprises a controllable oscillator and a frequency control circuit. The controllable oscillator is configured to generate an output signal that has a predefined frequency. The controllable oscillator is also configured with a plurality of operational states that are controlled by the frequency control circuit. Each operational state of the controllable oscillator defines a distinct frequency for the output signal of the controllable oscillator. The frequency control circuit receives the output signal of the controllable oscillator and determines the distinct frequency for the output signal that best approximates the predefined frequency.

Abstract: A polyphase filter for wireless communication systems includes at least two phase splitting filters each having a variable resistance across their respective outputs. The variable resistance can take any suitable form, such as a MOS transistor biased in the linear (triode) region, a bipolar differential pair, or a digitally switchable resistance. The phase adjustment required for a particular filter can be identified and adjusted through either a closed loop system or an open loop system. Adjustment of the variable resistance reduces quadrature error.

Abstract: A distributed active transformer on a semiconducting substrate is provided. The distributed active transformer includes an outer primary, a secondary disposed adjacent to the outer primary, and an inner primary disposed adjacent to the outer primary and the secondary. A plurality of first three terminal devices is coupled to the outer primary at a plurality of locations. A plurality of second three terminal devices coupled to the inner primary at a plurality of locations, and each second three terminal device is disposed opposite from and coupled to one of the plurality of first three terminal devices. A plurality of power control actuation circuits is also provided, where each power control actuation circuit is coupled to one of the first three terminal devices and the second three terminal devices.

Abstract: Various apparatus and method embodiments are disclosed.

Abstract: A translation loop signal upconverter is disclosed. Embodiments of the invention minimize nth order harmonics and spurious tones in the radio frequency output spectrum of a portable transceiver. In one embodiment, the invention is a signal upconverter, comprising a modulator configured to develop a modulated intermediate frequency (IF) signal at a fundamental frequency, the modulated IF signal also including a plurality of nth order components, a synchronous oscillator configured to receive the modulated IF signal, the synchronous oscillator also configured to operate at the fundamental frequency of the modulated IF signal, thereby providing an IF signal substantially free of the nth order components, and a translation loop having a phase locked loop, the translation loop configured to receive the IF signal output of the synchronous oscillator, and supply a radio frequency (RF) output signal to a power amplifier.

Abstract: A transmitter for a wireless handset having a modified translation loop architecture. The transmitter includes a VCO that generates a modulated transmit signal having a frequency fTx, and a modulated signal source that generates a modulated LO signal with a frequency fLO. A mixer mixes the transmit signal with the LO signal to produce an IF signal having a frequency fIF. A first divider divides the LO signal frequency fLO by an integer M to generate a first comparison signal having a frequency fCF. A second divider divides the IF signal frequency fIF, after it is multiplied by an integer K, by an integer N to generate a second comparison signal having a frequency fCF. The transmit and LO signal frequencies have the relationship f Tx = f LO ? KM ± N M . A phase detector coupled to the first and second comparison signals compares the phases of the signals and outputs a control voltage to the VCO proportional to any phase differences between the signals.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: Embodiments of the invention provide techniques for calibrating voltage-controlled oscillators (VCOs). Multiple VCOs may be disposed on a chip with the VCOs having different frequency ranges. The VCOs may be selected and tested to determine a desired VCO to use to tune to a selected channel frequency. Each of the VCOs has multiple possible varactor configurations. The varactor configurations of the desired VCO determined to be used to tune to the selected channel frequency can be selected and tested to determine a desired varactor configuration for the desired VCO. The desired VCO with the desired varactor configuration will preferably be able to produce a full range of desired frequencies corresponding to all channel frequencies desired.

Abstract: A quadrature mixer with an LO input is provided. The quadrature mixer receives a signal having a frequency FLO and a signal input having a frequency FSIG, and has an output that comprises an output impedance that is high at frequencies of |FLO?FSIG | and |FLO+FSIG| and low at other. A mixer coupled to the output impedance interacts with the output impedance such that an impedance presented at the signal input is high for signals at FSIG if FSIG is a predetermined signal frequency, and low at other frequencies.

Abstract: Embodiments of the invention provide techniques for calibrating voltage-controlled oscillators (VCOs). Multiple VCOs may be disposed on a chip with the VCOs having different frequency ranges. The VCOs may be selected and tested to determine a desired VCO to use to tune to a selected channel frequency. Each of the VCOs has multiple possible varactor configurations. The varactor configurations of the desired VCO determined to be used to tune to the selected channel frequency can be selected and tested to determine a desired varactor configuration for the desired VCO. The desired VCO with the desired varactor configuration will preferably be able to produce a full range of desired frequencies corresponding to all channel frequencies desired.

Abstract: A subharmonic mixer and a method of downconverting a received radio frequency signal is described. The subharmonic mixer of the present invention uses two stacks of switching cores with high order symmetry to reduce unwanted harmonic generation and uses transistors to improve headroom.

Abstract: Double balanced mixers having transistor pairs are affected by area mismatches between the transistors. The area mismatches can be represented as a ratio between the mixer core transistors that is directly related to voltage. Thus, an input voltage into one of the mixer core transistors in a transistor pair can compensate for the area mismatch. The compensation is achieved by a voltage track and hold feedback loop to one of the mixer core transistors.

Abstract: A programmable frequency divider capable of a 50% duty cycle at odd and even integer division ratios.