Abstract: Methods and devices for searching annotations in a document may include receiving a search request with at least one requested annotation classification to search for in a document. The methods and devices may include performing a search of the document for one or more annotations in the document matching the at least one annotation classification. The methods and devices may include generating a search result list with the one or more annotations in the document matching the at least one annotation classification. The methods and devices may include presenting the search result list.

Abstract: A problem with Internet access in a number of markets is the issue of data-limited network connections. Selective, on-demand consumption of web page data is provided. A user's browser presents a “light” version of a web page by loading compressed or low-fidelity versions of the web page images in place of the actual, higher-fidelity images. In the event that the user wishes to see the original higher-fidelity version of an image, clicking on the image or an associated icon loads the original-fidelity version of the image, replacing the low-fidelity version. The light version of the web page loads faster than would the original version of the web page, and requires less data to be downloaded when rendering the web page. This enables a user with a data-limited connection to select how he or she wishes to “spend” their data consumption.

Abstract: Methods and devices for searching annotations in a document may include receiving a search request with at least one requested annotation classification to search for in a document. The methods and devices may include performing a search of the document for one or more annotations in the document matching the at least one annotation classification. The methods and devices may include generating a search result list with the one or more annotations in the document matching the at least one annotation classification. The methods and devices may include presenting the search result list.

Abstract: A problem with Internet access in a number of markets is the issue of data-limited network connections. Selective, on-demand consumption of web page data is provided. A user's browser presents a “light” version of a web page by loading compressed or low-fidelity versions of the web page images in place of the actual, higher-fidelity images. In the event that the user wishes to see the original higher-fidelity version of an image, clicking on the image or an associated icon loads the original-fidelity version of the image, replacing the low-fidelity version. The light version of the web page loads faster than would the original version of the web page, and requires less data to be downloaded when rendering the web page. This enables a user with a data-limited connection to select how he or she wishes to “spend” their data consumption.

Abstract: Described herein is a method of web browser enabled annotation sharing comprising receiving information associated with the annotation, creating an anchored annotation based upon the received information associated with the annotation; and storing the anchored annotation. Further described herein is a method of retrieving an anchored annotation comprising receiving a request for an anchored annotation associated with particular content, retrieving anchored annotations associated with the particular content, filtering the retrieved anchored annotations; and, providing the filtered retrieved anchored annotations (e.g., to user(s) viewing the same content).

Abstract: Described herein is a method of web browser enabled annotation sharing comprising receiving information associated with the annotation, creating an anchored annotation based upon the received information associated with the annotation; and storing the anchored annotation. Further described herein is a method of retrieving an anchored annotation comprising receiving a request for an anchored annotation associated with particular content, retrieving anchored annotations associated with the particular content, filtering the retrieved anchored annotations; and, providing the filtered retrieved anchored annotations (e.g., to user(s) viewing the same content).

Abstract: A method, apparatus and computer program product are provided for facilitating a marketing interlock between businesses. Two or more businesses may enter into a co-marketing campaign in which a sponsoring entity funds an advertisement of a sponsored entity on a third party advertising system, such as a search engine. Marketing content of the sponsoring entity is inserted on the website of the sponsored entity. Traffic originating on the third party advertising system may therefore first be driven to the sponsored entity's website, and subsequently to the sponsoring entity's website, thereby achieving a mutually beneficial co-marketing relationship. Marketing relationships among complimentary businesses based on provided service and location may also be facilitated according to the methods provided.

Abstract: Techniques for validating business continuity preparedness of a virtual machine are described herein. The techniques may include executing a workload on a virtual machine and replicating the workload to another virtual machine. The replication may include generating one or more logs indicating changes that have occurred on the virtual machine and sending the one or more logs to the other virtual machine. Upon initiation of a failover, the workload may stop execution on the virtual machine and a log may be sent to the other virtual machine. The log may indicate changes occurring on the virtual machine to a point in time when execution of the workload stopped. The log may be stored to the other virtual machine. The workload may continue execution on the other virtual machine and may be replicated to the virtual machine.

Abstract: Disclosed is a full-chip level verification methodology that combines static timing analysis techniques with dynamic event-driven simulation. The specification discloses a capability to partition a multiple-clock design into various clock domains and surrounding asynchronous regions automatically and to determine the timing of the design on an instance by instance basis. Static timing analysis techniques can be leveraged to verify the synchronous cores of each clock domain. The asynchronous regions of the design and the interaction between synchronous cores of the clock domains are validated using detailed dynamic event-driven simulation without the burden of carrying the interior timing attributes of the synchronous cores that have already been verified.

Abstract: Disclosed is a full-chip level verification methodology that combines static timing analysis techniques with dynamic event-driven simulation. The specification discloses a capability to partition a multiple-clock design into various clock domains and surrounding asynchronous regions automatically and to determine the timing of the design on an instance by instance basis. Static timing analysis techniques can be leveraged to verify the synchronous cores of each clock domain. The asynchronous regions of the design and the interaction between synchronous cores of the clock domains are validated using detailed dynamic event-driven simulation without the burden of carrying the interior timing attributes of the synchronous cores that have already been verified.

Abstract: A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behavior, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur. If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values.

Abstract: A computer system includes an external unit governing a cache which generates a set-dirty request as a function of a coherence state of a block in the cache to be modified. The external unit modifies the block of the cache only if an acknowledgment granting permission is received from a memory management system responsive to the set-dirty request. The memory management system receives the set-dirty request, determines the acknowledgment based on contents of the plurality of caches and the main memory according to a cache protocol and sends the acknowledgment to the external unit in response to the set-dirty request. The acknowledgment will either grant permission or deny permission to set the block to the dirty state.

Abstract: According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more other versions of the information located in one or more caches. The process of filling the designated cache with the information is started by locating the information in the main memory and locating other versions of the information identified by the address in the caches. The validity of the information located in the main memory is determined after locating the other versions of the information. The process of filling the designated cache with the information located in the main memory is initiated before determining the validity of the information located in main memory. Thus, the memory reference is speculative.

Abstract: Load/store execution order violations in an out-of-order processor are reduced by determining whether a source address of a load instruction is the same as a destination address of a store instruction on which execution the load instruction depends. If they are the same, then execution of the load instruction is delayed until execution of the store instruction. In an system where virtual registers are mapped to a physical register, the physical registers mapped by the store and load instructions are compared. A table has entries corresponding to instructions in an instruction queue. In each table entry corresponding to a store instruction, the store instruction's destination address offset and physical register reference are saved. A load instruction's source address offset and physical reference are compared with each of the table entries corresponding to store instructions to determine whether a dependency exists.

Abstract: A technique controls memory access requests. The technique involves acquiring a first series of requests including a prefetch request for performing a prefetch operation that prefetches a first set of instructions from a memory, and adding a first entry in a request queue in response to the prefetch request. The first entry identifies the prefetch operation. The technique further involves attempting to retrieve a second set of instructions from a cache to create a cache miss, and generating, in response to the cache miss, a second series of requests including a fetch request for performing a fetch operation that fetches the second set of instructions from the memory to satisfy the cache miss. The technique further involves acquiring the second series of requests that includes the fetch request, and adding a second entry in the request queue in response to the fetch request. The second entry identifies the fetch operation.

Abstract: An architecture which splits primary and secondary cache memory buses and maintains cache hierarchy consistency without performing an explicit invalidation of the secondary cache tag. Two explicit rules are used to determine the status of a block read from the primary cache. In particular, if any memory reference subset matches a block in the primary cache, the associated secondary cache block is ignored. Secondly, if any memory reference subset matches a block in the miss address file, the associated secondary cache block is ignored. Therefore, any further references which subset match the first reference are not allowed to proceed until the fill back to main memory has been completed and the associated miss address file entry has been retired. This ensures that no agent in the host processor or an external agent can illegally use the stale secondary cache data.

Abstract: A multiprocessor system includes a plurality of processors, each processor having one or more caches local to the processor, and a memory controller connectable to the plurality of processors and a main memory. The memory controller manages the caches and the main memory of the multiprocessor system. A processor of the multiprocessor system is configurable to evict from its cache a block of data. The selected block may have a clean coherence state or a dirty coherence state. The processor communicates a notify signal indicating eviction of the selected block to the memory controller. In addition to sending a write victim notify signal if the selected block has a dirty coherence state, the processor sends a clean victim notify signal if the selected block has a clean coherence state.

Abstract: A memory management system couples processors to each other and to a main memory. Each processor may have one or more associated caches local to that processor. A system port of the memory management system receives a request from a source processor of the processors to access a block of data from the main memory. A memory manager of the memory management system then converts the request into a probe command having a data movement part identifying a condition for movement of the block out of a cache of a target processor and a next coherence state part indicating a next state of the block in the cache of the target processor.

Abstract: A computing apparatus connectable to a cache and a memory, includes a system port configured to receive an atomic probe command or a system data control response command having an address part identifying data stored in the cache which is associated with data stored in the memory and a next coherence state part indicating a next state of the data in the cache. The computing apparatus further includes an execution unit configured to execute the command to change the state of the data stored in the cache according to the next coherence state part of the command.

Abstract: A system manages access to caches connected to a plurality of processors in a multiprocessor system; the system including a system port and a memory manager. The system port is connectable to each of the plurality of processors and configured to receive a set-dirty request from one of the processors to modify a block of that processor's cache. The set-dirty request corresponds to a coherence state of the block of the cache. In response to the received set-dirty request, the memory manager directs sending, over the system port, of probes to the caches, (ii) receives cache state information, over the system port, responsive to the probes, (iii) determines an acknowledgment based on the received cache state information representing one of permission granted and permission denied to modify the block of the cache, and (iv) directs sending, over the system port, of the acknowledgment, to the processor.