Patents by Inventor Rahul Sahu
Rahul Sahu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10614865Abstract: Certain aspects of the present disclosure provide methods and apparatus for generating a negative boost voltage for memory write operations. One example memory circuit generally includes at least one memory bank, a write circuit coupled to the at least one memory bank, and a boost generation circuit coupled to the write circuit. The boost generation circuit generally includes a first node coupled to a reference potential node of the write circuit; a second node; a first capacitive element having a first terminal coupled to the first node of the boost generation circuit; a first switch configured to selectively couple the first node to a reference potential node for the memory circuit; and a second switch configured to selectively couple a second terminal of the first capacitive element to the second node of the boost generation circuit.Type: GrantFiled: October 17, 2018Date of Patent: April 7, 2020Assignee: QUALCOMM IncorporatedInventors: Shiba Narayan Mohanty, Rakesh Kumar Sinha, Rahul Sahu
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Publication number: 20190108872Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.Type: ApplicationFiled: October 6, 2017Publication date: April 11, 2019Inventors: Sharad Kumar GUPTA, Pradeep RAJ, Rahul SAHU, Mukund NARASIMHAN
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Patent number: 9928898Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.Type: GrantFiled: March 30, 2016Date of Patent: March 27, 2018Assignee: QUALCOMM IncorporatedInventors: Rahul Sahu, Sharad Kumar Gupta
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Patent number: 9916892Abstract: A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.Type: GrantFiled: March 2, 2017Date of Patent: March 13, 2018Assignee: QUALCOMM IncorporatedInventors: Pradeep Raj, Rahul Sahu, Mukund Narasimhan, Fahad Ahmed, Chulmin Jung
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Patent number: 9865337Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.Type: GrantFiled: March 22, 2017Date of Patent: January 9, 2018Assignee: QUALCOMM IncorporatedInventors: Fahad Ahmed, Mukund Narasimhan, Raghav Gupta, Pradeep Raj, Rahul Sahu, Po-Hung Chen, Chulmin Jung
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Publication number: 20170287551Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.Type: ApplicationFiled: March 30, 2016Publication date: October 5, 2017Inventors: Rahul SAHU, Sharad Kumar GUPTA
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Patent number: 9721650Abstract: A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.Type: GrantFiled: September 19, 2016Date of Patent: August 1, 2017Assignee: QUALCOMM IncorporatedInventors: Pradeep Raj, Sharad Kumar Gupta, Rahul Sahu, Lakshmikantha Holla Vakwadi
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Patent number: 9455028Abstract: A memory is provided with a write assist circuit that responds to an indication that a write operation on a modeled memory cell is successful by releasing a negative bit line boost.Type: GrantFiled: September 22, 2015Date of Patent: September 27, 2016Assignee: QUALCOMM IncorporatedInventor: Rahul Sahu
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Patent number: 9281055Abstract: A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.Type: GrantFiled: March 18, 2014Date of Patent: March 8, 2016Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Rahul Sahu, Dharmendra Kumar Rai
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Patent number: 9177635Abstract: Single-ended read circuits for SRAM devices are disclosed for high performance sub-micron designs. One embodiment is an SRAM device that includes a memory cell array and a bit line traversing the memory cell array for reading data from memory cells of the memory cell array. A read circuit coupled to the bit line translates data stored in a memory cell from a cell voltage of the memory cells to a peripheral voltage of an output of the SRAM device while bypassing a level shifter in the read data path.Type: GrantFiled: April 23, 2014Date of Patent: November 3, 2015Assignee: Avago Technologies General IP (Singapore) Pte LtdInventors: Donald Albert Evans, Rasoju Veerabadra Chary, Rajiv Kumar Roy, Rahul Sahu
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Patent number: 9177633Abstract: SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.Type: GrantFiled: March 5, 2014Date of Patent: November 3, 2015Assignee: Avago Technologies General IP (Singapore) Pte LtdInventors: Rajiv Kumar Roy, Rasoju Veerabadra Chary, Rahul Sahu
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Publication number: 20150302918Abstract: Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path.Type: ApplicationFiled: April 22, 2014Publication date: October 22, 2015Applicant: LSI CORPORATIONInventors: Rajiv Kumar Roy, Rasoju Veerabadra Chary, Dharmendra Kumar Rai, Rahul Sahu
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Publication number: 20150269990Abstract: A memory includes a number of storage elements connected to a pair of bit-lines, a bit-line pre-charging circuit, a sense amplifier connected to the pair of bit-lines through a column-select switch, a transition detection circuit connected to an output of the sense amplifier, and a local pre-charge control circuit connected to the transition detection circuit and having a local pre-charge control signal output connected to the bit-line pre-charging circuit.Type: ApplicationFiled: March 18, 2014Publication date: September 24, 2015Applicant: LSI CorporationInventors: Rahul Sahu, Dharmendra Kumar Rai
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Publication number: 20150255148Abstract: SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.Type: ApplicationFiled: March 5, 2014Publication date: September 10, 2015Applicant: LSI CORPORATIONInventors: Rajiv Kumar Roy, Rasoju Veerabadra Chary, Rahul Sahu
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Patent number: 9111637Abstract: Word line assist circuits are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a pair of word lines that traverse the memory cell array for selecting memory cells. The SRAM device further includes a pair of word line drivers, each coupled to one of the word lines. The SRAM device further includes a word line assist circuit coupled to the pair of word lines that receives an enable signal. Responsive to receiving the enable signal, the word line assist circuit assists the first word line driver and the second word line driver in transitioning their respective word lines from a logic level zero to a logic level one in response to a voltage differential between the word lines.Type: GrantFiled: May 12, 2014Date of Patent: August 18, 2015Assignee: Avago Technologies General IP Singapore) Pte LtdInventors: Rahul Sahu, Rajiv Kumar Roy, Rasoju Veerabadra Chary, Dharmendra Kumar Rai
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Publication number: 20150213881Abstract: Systems and methods presented herein provide for integrated read/write tracking in an SRAM device. In one embodiment, an SRAM device includes a clock, a memory cell array, a column of dummy bit cells operable to mirror bit line loading of the memory cell array, and a row of dummy bit cells operable to mirror word line loading of the memory cell array. The SRAM devices also includes a read/write tracking cell operable to track read operations from the memory cell array via the dummy bit cells, to track write operations to the memory cell array via the dummy bit cells, and to reset the clock based on the tracked read operations and the tracked write operations.Type: ApplicationFiled: February 13, 2014Publication date: July 30, 2015Applicant: LSI CORPORATIONInventors: Dharmendra Kumar Rai, Rahul Sahu
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Patent number: 9047936Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell.Type: GrantFiled: May 29, 2012Date of Patent: June 2, 2015Assignee: LSI CORPORATIONInventors: Vikash, Kamal Chandwani, Rahul Sahu
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Publication number: 20150138863Abstract: An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Applicant: LSI CORPORATIONInventors: Rajiv Kumar Roy, Donald Albert Evans, Rasoju Veerabadra Chary, Rahul Sahu
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Publication number: 20150138864Abstract: Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Applicant: LSI CORPORATIONInventors: Donald Albert Evans, Rasoju Veerabadra Chary, Rajiv Kumar Roy, Rahul Sahu
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Publication number: 20150085592Abstract: One embodiment is an apparatus that has a memory array, a discharge device, and a discharge assistance controller. The memory array has memory cells arranged in at least one column that is coupled to a read bit line, and the discharge device is configured to provide discharge assistance to the read bit line. The discharge assistance controller is configured to modify duration of the discharge assistance in correlation with capacitance of the read bit line.Type: ApplicationFiled: November 4, 2013Publication date: March 26, 2015Applicant: LSI CorporationInventors: Dharmendra Kumar Rai, Rahul Sahu