Patents by Inventor Raik Brinkmann
Raik Brinkmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11816410Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.Type: GrantFiled: August 30, 2022Date of Patent: November 14, 2023Assignee: Siemens Electronic Design Automation GmbhInventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
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Publication number: 20220414306Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.Type: ApplicationFiled: August 30, 2022Publication date: December 29, 2022Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
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Patent number: 11520963Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.Type: GrantFiled: June 19, 2018Date of Patent: December 6, 2022Assignee: ONESPIN SOLUTIONS GMBHInventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
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Publication number: 20200200820Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.Type: ApplicationFiled: June 19, 2018Publication date: June 25, 2020Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
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Patent number: 9344408Abstract: A method for formal verification of a digital circuit using a cloud-based verification engine. The method comprises extracting a proof problem from a design of a digital circuit with a local processor, reducing said proof problem to proof relevant data, encrypting said reduced proof problem, transmitting said encrypted reduced proof problem to a remote server, decrypting said encrypted reduced proof problem at said remote server, storing said reduced proof problem in a memory at said remote server, running a proof on said reduced proof problem at said remote server to generate a proof result; encrypting said proof result at said remote server; transmitting said encrypted proof result to said local processor; decrypting said encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using said decrypted proof result.Type: GrantFiled: April 25, 2014Date of Patent: May 17, 2016Assignee: Onespin Solutions GmbHInventors: Dominik Strasser, Gerrit Niesler, Mirko Fit, Raik Brinkmann
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Patent number: 9032345Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.Type: GrantFiled: March 28, 2014Date of Patent: May 12, 2015Assignee: Onespin Solutions GmbHInventor: Raik Brinkmann
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Publication number: 20140325669Abstract: A method for formal verification of a digital circuit using a cloud-based verification engine. The method comprises extracting a proof problem from a design of a digital circuit with a local processor, reducing said proof problem to proof relevant data, encrypting said reduced proof problem, transmitting said encrypted reduced proof problem to a remote server, decrypting said encrypted reduced proof problem at said remote server, storing said reduced proof problem in a memory at said remote server, running a proof on said reduced proof problem at said remote server to generate a proof result; encrypting said proof result at said remote server; transmitting said encrypted proof result to said local processor; decrypting said encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using said decrypted proof result.Type: ApplicationFiled: April 25, 2014Publication date: October 30, 2014Applicant: Onespin Solutions GmbHInventors: Dominik Strasser, Gerrit Niesler, Mirko Fit, Raik Brinkmann
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Publication number: 20140215418Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.Type: ApplicationFiled: March 28, 2014Publication date: July 31, 2014Inventor: Dr. Raik Brinkmann
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Patent number: 8701060Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.Type: GrantFiled: April 26, 2012Date of Patent: April 15, 2014Assignee: Onespin Solutions, GmbHInventor: Raik Brinkmann
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Publication number: 20130019217Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.Type: ApplicationFiled: April 26, 2012Publication date: January 17, 2013Inventor: Raik Brinkmann