Patents by Inventor Raik Brinkmann

Raik Brinkmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11816410
    Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: November 14, 2023
    Assignee: Siemens Electronic Design Automation Gmbh
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
  • Publication number: 20220414306
    Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
  • Patent number: 11520963
    Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 6, 2022
    Assignee: ONESPIN SOLUTIONS GMBH
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
  • Publication number: 20200200820
    Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Application
    Filed: June 19, 2018
    Publication date: June 25, 2020
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
  • Patent number: 9344408
    Abstract: A method for formal verification of a digital circuit using a cloud-based verification engine. The method comprises extracting a proof problem from a design of a digital circuit with a local processor, reducing said proof problem to proof relevant data, encrypting said reduced proof problem, transmitting said encrypted reduced proof problem to a remote server, decrypting said encrypted reduced proof problem at said remote server, storing said reduced proof problem in a memory at said remote server, running a proof on said reduced proof problem at said remote server to generate a proof result; encrypting said proof result at said remote server; transmitting said encrypted proof result to said local processor; decrypting said encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using said decrypted proof result.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 17, 2016
    Assignee: Onespin Solutions GmbH
    Inventors: Dominik Strasser, Gerrit Niesler, Mirko Fit, Raik Brinkmann
  • Patent number: 9032345
    Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 12, 2015
    Assignee: Onespin Solutions GmbH
    Inventor: Raik Brinkmann
  • Publication number: 20140325669
    Abstract: A method for formal verification of a digital circuit using a cloud-based verification engine. The method comprises extracting a proof problem from a design of a digital circuit with a local processor, reducing said proof problem to proof relevant data, encrypting said reduced proof problem, transmitting said encrypted reduced proof problem to a remote server, decrypting said encrypted reduced proof problem at said remote server, storing said reduced proof problem in a memory at said remote server, running a proof on said reduced proof problem at said remote server to generate a proof result; encrypting said proof result at said remote server; transmitting said encrypted proof result to said local processor; decrypting said encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using said decrypted proof result.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 30, 2014
    Applicant: Onespin Solutions GmbH
    Inventors: Dominik Strasser, Gerrit Niesler, Mirko Fit, Raik Brinkmann
  • Publication number: 20140215418
    Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.
    Type: Application
    Filed: March 28, 2014
    Publication date: July 31, 2014
    Inventor: Dr. Raik Brinkmann
  • Patent number: 8701060
    Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: April 15, 2014
    Assignee: Onespin Solutions, GmbH
    Inventor: Raik Brinkmann
  • Publication number: 20130019217
    Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.
    Type: Application
    Filed: April 26, 2012
    Publication date: January 17, 2013
    Inventor: Raik Brinkmann