Patents by Inventor Raiyomand F. Aspandiar

Raiyomand F. Aspandiar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11715928
    Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 1, 2023
    Assignee: Intel Corporation
    Inventors: Priyanka Dobriyal, Susheel G. Jadhav, Ankur Agrawal, Quan A. Tran, Raiyomand F. Aspandiar, Kenneth M. Brown
  • Publication number: 20230084375
    Abstract: An apparatus comprising an integrated circuit chip comprising a first surface region and a second surface region adjacent to the first surface region; a substrate coupled to the integrated circuit chip through a plurality of connections comprising solder; and underfill between the substrate and the integrated circuit chip, wherein the underfill contacts the second surface region, but does not contact the first surface region.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Applicant: Intel Corporation
    Inventors: Priyanka Dobriyal, Ankur Agrawal, Anna M. Prakash, Ann J. Xu, Jimin Yao, Raiyomand F. Aspandiar, Lesley A. Polka Wood, Abigail G. Agwai, Kayleen L. E. Helms
  • Publication number: 20210066882
    Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Applicant: INTEL CORPORATION
    Inventors: Priyanka Dobriyal, Susheel G. Jadhav, Ankur Agrawal, Quan A. Tran, Raiyomand F. Aspandiar, Kenneth M. Brown
  • Patent number: 10356912
    Abstract: An electronic system includes a printed circuit board (PCB), a component affixed to the PCB, and a conformal coating layer on the PCB and the component. The conformal coating layer includes parylene. Furthermore, the electronic system includes an underfill layer adjacent to the conformal coating layer, filling a gap between the PCB and the component. Other embodiments being described and/or claimed.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Priyanka Dobriyal, Suriyakala Ramalingam, Chester C. Lee, Raiyomand F. Aspandiar
  • Publication number: 20180070456
    Abstract: An electronic system may include a printed circuit board (PCB), a component affixed to the PCB, and a conformal coating layer on the PCB and the component. The conformal coating layer may include parylene. Furthermore, the electronic system may include an underfill layer adjacent to the conformal coating layer, filling a gap between the PCB and the component. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Inventors: Priyanka Dobriyal, Suriyakala Ramalingam, Chester C. Lee, Raiyomand F. Aspandiar
  • Patent number: 7251880
    Abstract: A method and apparatus are provided for determining whether solder used during assembly of a printed circuit board is lead-free or not. This may include providing a pad on the printed circuit board and placing solder on the pad in a predetermined pattern. The solder may be heated so as to create reflow. The solder may later be examined to determine if the solder is lead-free.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 7, 2007
    Assignee: Intel Corporation
    Inventors: Tom E. Pearson, George Arrigotti, Christopher D. Combs, Raiyomand F. Aspandiar
  • Patent number: 7183496
    Abstract: An anchoring mechanism and method are provided for securing a component to a printed circuit board. The anchoring mechanism may include a loop, a first leg extending from the loop, and a second leg extending from the loop. The first leg may mount through a first hole of the printed circuit board and include a compressible section to compress when inserted into the first hole and to expand after passing through the first hole. The compressible section of the first leg may support solder between the anchoring mechanism and the first hole. Likewise, the second leg may mount through a second hole of the printed circuit board and include a compressible section to compress when inserted into the second hole and to expand after passing through the second hole. The compressible section of the second leg may support solder between the anchoring mechanism and the second hole.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: George Arrigotti, Tom E. Pearson, Raiyomand F. Aspandiar, Christopher D. Combs
  • Patent number: 6917524
    Abstract: A mechanism and method are provided for assembling a printed circuit board having a first surface, a second surface and an edge. The printed circuit board may include at least one female member to receive a corresponding male member. The mechanism may include an extension board having an edge to couple to the edge of the printed circuit board. The extension board may include a male member to extend from the edge of the extension board and to couple to the at least one male member so as to couple the extension board to the printed circuit board.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: July 12, 2005
    Assignee: Intel Corporation
    Inventors: Tom E. Pearson, George Arrigotti, Christopher D. Combs, Raiyomand F. Aspandiar
  • Publication number: 20040207076
    Abstract: An anchoring mechanism and method are provided for securing a component to a printed circuit board. The anchoring mechanism may include a loop, a first leg extending from the loop, and a second leg extending from the loop. The first leg may mount through a first hole of the printed circuit board and include a compressible section to compress when inserted into the first hole and to expand after passing through the first hole. The compressible section of the first leg may support solder between the anchoring mechanism and the first hole. Likewise, the second leg may mount through a second hole of the printed circuit board and include a compressible section to compress when inserted into the second hole and to expand after passing through the second hole. The compressible section of the second leg may support solder between the anchoring mechanism and the second hole.
    Type: Application
    Filed: May 11, 2004
    Publication date: October 21, 2004
    Inventors: George Arrigotti, Tom E. Pearson, Raiyomand F. Aspandiar, Christopher D. Combs
  • Patent number: 6801436
    Abstract: A mechanism and method are provided for assembling a printed circuit board having a first surface, a second surface and an edge. The printed circuit board may include at least one female member to receive a corresponding male member. The mechanism may include an extension board having an edge to couple to the edge of the printed circuit board. The extension board may include a male member to extend from the edge of the extension board and to couple to the at least one male member so as to couple the extension board to the printed circuit board.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: October 5, 2004
    Assignee: Intel Corporation
    Inventors: Tom E. Pearson, George Arrigotti, Christopher D. Combs, Raiyomand F. Aspandiar
  • Patent number: 6791035
    Abstract: An interposer to couple a microelectronic device package to a motherboard is formed from a PCB substrate. Multiple via holes are drilled through a copper-clad PCB substrate and then coated inside with copper. The copper surface coating is etched to form multiple traces. In one embodiment, the substrate is cut through each row of via holes and between each row of via holes to produce multiple individual beam-and-trace interposers. Two or more such interposers may be affixed together to form a beam-and-trace interposer array. Alternatively, the substrate is not cut into strips, and each via hole is filled completely with a conductive material to form an array of solid conductive columns through the substrate.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Thomas E. Pearson, George L. Arrigotti, Raiyomand F. Aspandiar, Christopher D. Combs
  • Patent number: 6734371
    Abstract: An anchoring mechanism and method are provided for securing a component to a printed circuit board. The anchoring mechanism may include a loop, a first leg extending from the loop, and a second leg extending from the loop. The first leg may mount through a first hole of the printed circuit board and include a compressible section to compress when inserted into the first hole and to expand after passing through the first hole. The compressible section of the first leg may support solder between the anchoring mechanism and the first hole. Likewise, the second leg may mount through a second hole of the printed circuit board and include a compressible section to compress when inserted into the second hole and to expand after passing through the second hole. The compressible section of the second leg may support solder between the anchoring mechanism and the second hole.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 11, 2004
    Assignee: Intel Corporation
    Inventors: George Arrigotti, Tom E. Pearson, Raiyomand F. Aspandiar, Christopher D. Combs
  • Patent number: 6700800
    Abstract: A retainer for a circuit board and method for using the same are provided. In one embodiment, a circuit board assembly includes a circuit board, an electronic component, a plurality of electric contacts between the circuit board and the electronic component, and a retainer. The retainer has a first component secured to the circuit board and a second component secured to the electronic component. The retainer allows for movement of the electronic component in a first direction towards the circuit board while simultaneously preventing movement of the circuit board and the electronic component in a second direction away from one another when the electric contacts melt.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: March 2, 2004
    Assignee: Intel Corporation
    Inventors: Christopher Combs, Arjang Fartash, Tom E. Pearson, Raiyomand F. Aspandiar
  • Publication number: 20040003496
    Abstract: An interposer to couple a microelectronic device package to a motherboard is formed from a PCB substrate. Multiple via holes are drilled through a copper-clad PCB substrate and then coated inside with copper. The copper surface coating is etched to form multiple traces In one embodiment, the substrate is cut through each row of via holes and between each row of via holes to produce multiple individual beam-and-trace interposers. Two or more such interposers may be affixed together to form a beam-and-trace interposer array. Alternatively, the substrate is not cut into strips, and each via hole is filled completely with a conductive material to form an array of solid conductive columns through the substrate.
    Type: Application
    Filed: July 1, 2003
    Publication date: January 8, 2004
    Applicant: Intel Corporation
    Inventors: Thomas E. Pearson, George L. Arrigotti, Raiyomand F. Aspandiar, Christopher D. Combs
  • Publication number: 20030231481
    Abstract: A retainer for a circuit board and method for using the same are provided. In one embodiment, a circuit board assembly includes a circuit board, an electronic component, a plurality of electric contacts between the circuit board and the electronic component, and a retainer. The retainer has a first component secured to the circuit board and a second component secured to the electronic component. The retainer allows for movement of the electronic component in a first direction towards the circuit board while simultaneously preventing movement of the circuit board and the electronic component in a second direction away from one another when the electric contacts melt.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 18, 2003
    Inventors: Christopher Combs, Arjang Fartash, Tom E. Pearson, Raiyomand F. Aspandiar
  • Patent number: 6651869
    Abstract: A method of wave soldering a circuit board while avoiding reflow of a solder joint on the topside of the board from heat conducted from the solder wave through at least one via in the board in heat conducting relation with the topside solder joint, comprises subjecting the circuit board to a solder wave and absorbing heat being conducted from the solder wave through the at least one via with an endothermic material in the via hole which undergoes a heat absorbing reaction. The heat absorbing reaction of the endothermic material is preferably a phase change, such as melting. The melted endothermic material is retained in the via hole during wave soldering by capillary forces and a cap on the lower end of the via hole. A disclosed method of making the circuit board includes locating the endothermic material in the via hole by inserting a preform of the endothermic material into the via hole or hot dispensing the endothermic material into the via hole.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: November 25, 2003
    Assignee: Intel Corporation
    Inventors: Raiyomand F. Aspandiar, Tom E. Pearson, Christopher Combs
  • Publication number: 20030156396
    Abstract: An interposer to couple a microelectronic device package to a motherboard is formed from a PCB substrate. Multiple via holes are drilled through a copper-clad PCB substrate and then coated inside with copper. The copper surface coating is etched to form multiple traces. In one embodiment, the substrate is cut through each row of via holes and between each row of via holes to produce multiple individual beam-and-trace interposers. Two or more such interposers may be affixed together to form a beam-and-trace interposer array. Alternatively, the substrate is not cut into strips, and each via hole is filled completely with a conductive material to form an array of solid conductive columns through the substrate.
    Type: Application
    Filed: February 21, 2002
    Publication date: August 21, 2003
    Inventors: Thomas E. Pearson, George L. Arrigotti, Raiyomand F. Aspandiar, Christopher D. Combs
  • Publication number: 20030124885
    Abstract: A zero mounting force solder-free connector/component and method.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Inventors: Christopher D. Combs, George Arrigotti, Raiyomand F. Aspandiar, Tom E. Pearson
  • Patent number: 6552275
    Abstract: An apparatus including a substrate, and a surface mount component coupled with a top surface of the substrate, where the component includes side surfaces and a bottom surface, and the bottom surface is disposed adjacent to the top surface of the substrate. The side surfaces and the bottom surface of the surface mount component define a lower portion therebetween, the lower portion recessed away from the bottom component surface to allow solder to flow freely around a mounting lead of the surface mount component, for example, during the reflow process.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: April 22, 2003
    Assignee: Intel Corporation
    Inventors: Arjang Fartash, Raiyomand F. Aspandiar
  • Publication number: 20030062192
    Abstract: A method and apparatus are provided for determining whether solder used during assembly of a printed circuit board is lead-free or not. This may include providing a pad on the printed circuit board and placing solder on the pad in a predetermined pattern. The solder may be heated so as to create reflow. The solder may later be examined to determine if the solder is lead-free.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Tom E. Pearson, George Arrigotti, Christopher D. Combs, Raiyomand F. Aspandiar