Patents by Inventor Raj K. Bansal
Raj K. Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145425Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
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Publication number: 20240088100Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.Type: ApplicationFiled: September 13, 2023Publication date: March 14, 2024Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
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Publication number: 20240072002Abstract: A semiconductor device assembly can include an assembly substrate having a top surface with a die stack thereat. The die stack can include a first and a second die, and each dies can include a die substrate with a top and a bottom surface. The top surface can include a first region a first distance from the bottom surface, and a second region a second distance, greater than the first distance, from the bottom surface and with a bond pad thereat. The bottom surface of the first die can bond with the top surface of the assembly substrate, and the bottom surface of the second die can bond with the first region of the first die top surface. In some embodiments, the assembly can further include additional die stacks and/or additional dies within one or more die stacks.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Inventor: Raj K. Bansal
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Patent number: 11876068Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.Type: GrantFiled: September 29, 2022Date of Patent: January 16, 2024Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
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Publication number: 20240014083Abstract: A method of making a semiconductor device assembly is provided. The method comprises attaching a first semiconductor device to an upper surface of a substrate and disposing a stencil over the upper surface of the substrate. The stencil includes (i) an opening and (ii) a cavity in which the first semiconductor device is disposed. The method further comprises screen-printing an epoxy material into the opening and onto the upper surface of the substrate, removing the stencil, and planarizing an upper surface of the epoxy material to form an epoxy spacer.Type: ApplicationFiled: July 3, 2023Publication date: January 11, 2024Inventors: Hem P. Takiar, Raj K. Bansal, Jian Wei Lim, Li Wang, Jungbae Lee
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Patent number: 11810822Abstract: Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.Type: GrantFiled: September 22, 2021Date of Patent: November 7, 2023Assignee: Micron Technology, Inc.Inventors: Shigeru Sugioka, Keizo Kawakita, Raj K. Bansal, Tsung Che Tsai
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Publication number: 20230326867Abstract: Methods, systems, and devices for techniques for forming a device with scribe asymmetry are described. Circuits (e.g., arrays of memory cells) may be printed on a wafer and separated by scribes of various widths to increase an array efficiency of a fabrication process. For example, a scribe that extends in a first direction may have a width in a second direction. A first subset of scribes may have a first width, where one or more structures may be placed in the first subset of scribes to facilitate die testing and integration. A second subset of scribes may have a second width. In some examples, the structures may not be placed in the second subset of scribes and, accordingly, the second width may be less than the first width.Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Inventors: Anna Maria Conti, Raj K. Bansal
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Patent number: 11769756Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.Type: GrantFiled: June 27, 2022Date of Patent: September 26, 2023Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
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Publication number: 20230290684Abstract: Structures and methods for separating semiconductor wafers into individual dies are disclosed. A semiconductor wafer or panel can include a crack assist structure in a scribe junction. The crack assist structure can include a plurality of vertical walls extending at least partially through a thickness of the wafer. In some embodiments, the plurality of vertical walls can be coupled to a weak interface. The weak interface can guide cracks that form during the dicing process in a direction along the walls, away from active circuitry. After dicing, the resulting semiconductor devices can include a plurality of vertical walls extending at least partially through a thickness of the semiconductor device. Each of the plurality of vertical walls can include at least a portion extending substantially parallel to a sidewall of the semiconductor device.Type: ApplicationFiled: March 9, 2022Publication date: September 14, 2023Inventors: Wei Chang Wong, Radhakrishna Kotti, Raj K. Bansal, Youngik Kwon, Po Chih Yang, Venkateswarlu Bhavanasi
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Patent number: 11705432Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.Type: GrantFiled: July 1, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
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Publication number: 20230090041Abstract: Apparatuses including structures in scribe lines are described. An example apparatus includes: a first chip and a second chip; a scribe region between the first chip and the second chip; a crack guide region in the scribe region, the crack guide region including a dicing line along which the first chip and the second chip are to be divided; and a structure disposed in the crack guide region and extending along the dicing line.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: Micron Technology, Inc.Inventors: SHIGERU SUGIOKA, KEIZO KAWAKITA, RAJ K. BANSAL, TSUNG CHE TSAI
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Publication number: 20230061258Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.Type: ApplicationFiled: April 11, 2022Publication date: March 2, 2023Inventors: Koichi Kawai, Raj K. Bansal, Takehiro Hasegawa, Chang H. Siau
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Publication number: 20230055425Abstract: A semiconductor device has first and second dies forming a die stack. Molding material encapsulates the die stack and forms an upper molded surface of the die stack. First conductive traces are coupled to the first die and extend from between the first and second die to corresponding first via locations in the molding material beyond a first side edge of the die stack. Second conductive traces coupled to an active surface of the second die opposite the first die extend to corresponding second via locations. Each first via location is vertically aligned with one of the second via locations. Through mold vias extend through the molding material between vertically aligned via locations to contact with corresponding conductive traces of the first and second dies, while the molding material that extends between the first conductive traces and the upper molded surface is free from any TMV.Type: ApplicationFiled: September 17, 2021Publication date: February 23, 2023Inventors: Travis M. Jensen, Raj K. Bansal
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Publication number: 20230026960Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.Type: ApplicationFiled: September 29, 2022Publication date: January 26, 2023Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
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Publication number: 20230011222Abstract: According to one or more embodiments, a method of manufacturing a semiconductor device including a plurality of main circuit regions arranged in a matrix and a scribe region provided between the main circuit regions is provided. The method includes: forming a first insulating film; forming a low-k film; forming a plurality of penetrating portions penetrating through the low-k film; and forming a second insulating film under low-coverage film-forming conditions to form cavities in the plurality of through-holes.Type: ApplicationFiled: September 26, 2022Publication date: January 12, 2023Applicant: Micron Technology, Inc.Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita, Raj K. Bansal
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Patent number: 11502053Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.Type: GrantFiled: November 24, 2020Date of Patent: November 15, 2022Assignee: Micron Technology, Inc.Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
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Publication number: 20220328456Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.Type: ApplicationFiled: June 27, 2022Publication date: October 13, 2022Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
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Patent number: 11456253Abstract: A semiconductor device includes a main circuit region; and a scribe region surrounding the main circuit region; wherein the main circuit region and the scribe region comprises first and second insulating films and a low-k film formed therebetween; and wherein the low-k film of the scribe region includes a plurality of cavities lining along a border between the main circuit region and the scribe region.Type: GrantFiled: May 11, 2020Date of Patent: September 27, 2022Assignee: Micron Technology, Inc.Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita, Raj K. Bansal
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Patent number: 11450645Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.Type: GrantFiled: November 24, 2020Date of Patent: September 20, 2022Assignee: Micron Technology, Inc.Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
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Publication number: 20220165701Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.Type: ApplicationFiled: November 24, 2020Publication date: May 26, 2022Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock