Abstract: A method and architecture to write data between a source and destination by memory mapped writes or streaming packets between any of a host, a peripheral or a sub-peripheral device. A stream address is used to write the data to a memory of the destination without the source being aware of physical addresses of destination memory, i.e., memory descriptors or pointers are not used, allowing the destination to manage its own memory. The stream address may enable streaming data packets over interconnects that may not allow packet streaming by dividing a data packet into data chunks and including a stream address for each chunk. The stream address for a given packet includes a repeated first portion indicating the destination and a varied second portion indicating variable information for each data chunk such as start of packet (SoP) and end of packet (EoP) identifiers.

Abstract: A coded signal is received via a physical channel. The coded signal is encoded by a parity check matrix. In some examples, the coded signal is low density parity check-encoded. The coded signal is decoded to determine a result signal. Said decoding alternatingly updates, for each one of a number of iterations, bit node values representing bits of the result signal and check node values representing constrains of the parity check matrix. In some examples, the decoding determines the result signal at a first precision and updates at least partly at a second precision which is lower than the first precision. In further examples, the number of iterations is dynamically adjusted.

Abstract: A coded signal (356, 361, 362, 363) is received via a physical link (151) and decoded (322, 323, 324). A link loss of the physical link (151) is detected based on at least one of the coded signal (356, 361, 362, 363) and said decoding (322, 323, 324).

Abstract: A method and architecture to write data between a source and destination by memory mapped writes or streaming packets between any of a host, a peripheral or a sub-peripheral device. A stream address is used to write the data to a memory of the destination without the source being aware of physical addresses of destination memory, i.e., memory descriptors or pointers are not used, allowing the destination to manage its own memory. The stream address may enable streaming data packets over interconnects that may not allow packet streaming by dividing a data packet into data chunks and including a stream address for each chunk. The stream address for a given packet includes a repeated first portion indicating the destination and a varied second portion indicating variable information for each data chunk such as start of packet (SoP) and end of packet (EoP) identifiers.

Abstract: A Digital Subscriber Line, DSL/G.fast/G.hn, transceiver comprising a plurality of first interfaces configured to transmit data packet streams in a downlink direction to different subscribers and to receive data packet streams from the different subscribers, a second interface configured to transmit data packet streams in an uplink direction to a passive optical network element, and at least one processing unit configured to detect a physical layer indicator of a loss of signal of one of the first interfaces received at a physical layer at said one first interface, wherein when the at least one processing unit detects the physical layer indicator for said one first interface, the second interface transmits the physical layer indicator in the uplink direction to the passive optical network element.

Abstract: A coded signal is received via a physical channel. The coded signal is encoded by a parity check matrix. In some examples, the coded signal is low density parity check-encoded. The coded signal is decoded to determine a result signal. Said decoding alternatingly updates, for each one of a number of iterations, bit node values representing bits of the result signal and check node values representing constrains of the parity check matrix. In some examples, the decoding determines the result signal at a first precision and updates at least partly at a second precision which is lower than the first precision. In further examples, the number of iterations is dynamically adjusted.

Abstract: A Digital Subscriber Line, DSL/G.fast/G.hn, transceiver comprising a plurality of first interfaces configured to transmit data packet streams in a downlink direction to different subscribers and to receive data packet streams from the different subscribers, a second interface configured to transmit data packet streams in an uplink direction to a passive optical network element, and at least one processing unit configured to detect a physical layer indicator of a loss of signal of one of the first interfaces received at a physical layer at said one first interface, wherein when the at least one processing unit detects the physical layer indicator for said one first interface, the second interface transmits the physical layer indicator in the uplink direction to the passive optical network element.

Abstract: An access point and a method for transmitting data through an access point are disclosed, In one embodiment the access point includes a MAC processor configured to process and output a single transmit data stream, and a physical layer (PHY) processor configured to split the single transmit data stream in a plurality of transmit data streams, the physical layer (PHY) processor further configured to process a first group of one or more channel paths for the first set of one or more transmit data streams according to the first mode of operation and a second group of one or more channel paths for the second set of one or more transmit data streams according to the second mode of operation.

Abstract: A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are grouped, and Trellis encoding is performed only of the members of a group. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the computational and memory requirements of the encoder and decoder. Furthermore, Trellis decoding errors are not propagated between the groups.

Abstract: A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such that, when one of the integrated circuits requires a portion of the program, which is contained in its own program memory, it extracts it from the program memory and uses it, but when it requires a portion of the program, which is not contained in its own program memory, it reads it from the program memory of one of the other integrated circuits into its second memory and runs that portion of the program from there. In one example, the system is a line card, and the program is specific to one DSL protocol.

Abstract: A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are grouped, and Trellis encoding is performed only of the members of a group. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the computational and memory requirements of the encoder and decoder. Furthermore, Trellis decoding errors are not propagated between the groups.

Abstract: A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are grouped, and Trellis encoding is performed only of the members of a group. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the computational and memory requirements of the encoder and decoder. Furthermore, Trellis decoding errors are not propagated between the groups.

Abstract: A line card is proposed in which one or more DMT processing modules 1 communicate with a data link layer platform, such as an ATM, POSPHY or Ethernet processor. The data relating to a single symbol is transmitted between the data link layer platform and a given one of DMT processing modules in a plurality of data portions spaced apart in time. The data portions relating to different channels of a given DMT processing module (or to different DMT processing modules) are interleaved in time. Since the data portions of a given symbol are spaced apart in time, the data relating to a single symbol is transmitted over a longer time period than in conventional devices which reduces the effective burstiness of the traffic, and thus reduces the memory requirements of the data link layer platform.

Abstract: Embodiments of an access point for an expanded wireless local area network are described and depicted.

Abstract: A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such that, when one of the integrated circuits requires a portion of the program, which is contained in its own program memory, it extracts it from the program memory and uses it, but when it requires a portion of the program, which is not contained in its own program memory, it reads it from the program memory of one of the other integrated circuits into its second memory and runs that portion of the program from there. In one example, the system is a line card, and the program is specific to one DSL protocol.

Abstract: A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such that, when one of the integrated circuits requires a portion of the program, which is contained in its own program memory, it extracts it from the program memory and uses it, but when it requires a portion of the program, which is not contained in its own program memory, it reads it from the program memory of one of the other integrated circuits into its second memory and runs that portion of the program from there. In one example, the system is a line card, and the program is specific to one DSL protocol.

Abstract: Systems and methods for processing data signals are described. In one implementation, a demodulator and a first decoder unit, such as a convolutional encoder or a quadrature amplitude modulation decoder, for receiving the output of the demodulator, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal are provided. The decoded signal may be passed through a de-interleaving unit to form a de-interleaved signal. The first location signal may be passed to an identifier unit which receives it, and from it produces a second error indication signal indicative of the errors in the de-interleaved signal. The de-interleaved signal and the second error indication signal may be transmitted to a redundancy decoder, where the signals may be used to perform redundancy decoding.

Abstract: A new protocol is proposed for transmission of data through lines such as telephone lines. The tones of a signal are associated into groups 10, 11, and tone ordering, gain selection, and/or bit swapping within the processing system are done within the members of a group 10, 11. This idea is applicable both to tone ordering etc., following the training stage, and also to the dynamic configuration changes subsequently, for example, bit swapping. The computational cost of coding and decoding the data is reduced (compared to treating all the tones of a given direction equivalently), and the invention makes it possible to significantly reduce the memory requirements of the encoder and decoder.

Abstract: A system for processing a data signal (such as an ADSL or VDSL signal) includes a first decoder unit, such as a convolutional decoder or a QAM decoder, for receiving the data signal, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal. A redundancy decoder employs the decoded signal and the first error indication signal (or transformed versions thereof) to perform redundancy decoding.

Abstract: A method of controlling a data flow, a transmitter and a data transmission system are described. For example, in a method of controlling a data flow of a transmitter, first data is received at a first interface. The first data is buffered in a buffer. The first data is output via a second interface. Information is determined regarding an estimated amount of second data comprising payload data output via the first interface until a filling level of the buffer will reach a predetermined threshold. An amount of the payload data output via the first interface is adjusted based on the information. The payload data is then output via the first interface. Similarly, a transmitter includes an interface to output payload data and a control signal, and a buffer to buffer further data received via the interface wherein the control signal controls a flow of said further data.