Patents by Inventor Raj Ramanujan
Raj Ramanujan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978491Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.Type: GrantFiled: September 24, 2021Date of Patent: May 7, 2024Assignee: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin, Raj Ramanujan
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Patent number: 11972822Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).Type: GrantFiled: December 15, 2021Date of Patent: April 30, 2024Assignee: SanDisk Technologies LLCInventors: Martin Hassner, Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin, Raj Ramanujan
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Patent number: 11650765Abstract: Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.Type: GrantFiled: October 29, 2021Date of Patent: May 16, 2023Assignee: QUALCOMM IncorporatedInventors: Raj Ramanujan, Kuljit Singh Bains, Liyong Wang, Wesley Queen
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Publication number: 20230100600Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. The current-force referenced read provides a very fast read of the memory cells and can be successful in most cases. The current-force SRR provides a more accurate read in the event that the current-force referenced read is not successful. Moreover, the current-force referenced read may use less power than the current-force SRR. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin, Raj Ramanujan
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Publication number: 20230101414Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).Type: ApplicationFiled: December 15, 2021Publication date: March 30, 2023Applicant: SanDisk Technologies LLCInventors: Martin Hassner, Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin, Raj Ramanujan
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Publication number: 20220407803Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.Type: ApplicationFiled: May 17, 2022Publication date: December 22, 2022Applicant: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj Ramanujan, Brian Slechta
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Patent number: 11343177Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.Type: GrantFiled: October 30, 2020Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj Ramanujan, Brian Slechta
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Publication number: 20220050600Abstract: Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.Type: ApplicationFiled: October 29, 2021Publication date: February 17, 2022Inventors: Raj RAMANUJAN, Kuljit Singh Bains, Liyong Wang, Wesley Queen
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Patent number: 11194524Abstract: A processing system for performing persistent write operations comprises a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host. Persistent Write completion indications may be provided to the host in a different order from an order in which corresponding commands were received. Statuses of Persistent Write commands may be maintained in a completed bitmap or a pending bitmap. A FLUSH command may be provided to indicate that all prior writes buffered in volatile media are to be pushed to non-volatile or persistent memory.Type: GrantFiled: September 15, 2017Date of Patent: December 7, 2021Assignee: Qualcomm IncorporatedInventors: Raj Ramanujan, Kuljit Singh Bains, Liyong Wang, Wesley Queen
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Patent number: 11099784Abstract: Apparatuses and techniques are described for reading crosspoint arrays of memory cells with high bandwidth and a relatively small page buffer. Multiple crosspoint arrays (XPAs) are read in parallel, with one memory cell per XPA being read, in a bank of XPAs. To reduce the read time, a row can be selected for the XPAs, after which memory cells in different columns are read, one column at a time, while the same row is selected. This avoids the need to transmit commands and a row address for re-selecting the row in each successive read operation. The XPAs may be ungrouped, or one XPA may be accessible at a time in a group. In one option, the XPAs are arranged in sets, either individually or in groups, and one set is accessible at a time.Type: GrantFiled: December 17, 2019Date of Patent: August 24, 2021Assignee: SanDisk Technologies LLCInventors: Won Ho Choi, Ward Parkinson, Raj Ramanujan, Martin Lueker-Boden
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Publication number: 20210181979Abstract: Apparatuses and techniques are described for reading crosspoint arrays of memory cells with high bandwidth and a relatively small page buffer. Multiple crosspoint arrays (XPAs) are read in parallel, with one memory cell per XPA being read, in a bank of XPAs. To reduce the read time, a row can be selected for the XPAs, after which memory cells in different columns are read, one column at a time, while the same row is selected. This avoids the need to transmit commands and a row address for re-selecting the row in each successive read operation. The XPAs may be ungrouped, or one XPA may be accessible at a time in a group. In one option, the XPAs are arranged in sets, either individually or in groups, and one set is accessible at a time.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Ward Parkinson, Raj Ramanujan, Martin Lueker-Boden
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Patent number: 11016669Abstract: In non-energy-backed memory with persistent storage, a complex protocol is required to handle persistent writes. To address this issue, it is proposed to provide a simple protocol to handle persistent writes in energy-backed memory with persistent storage.Type: GrantFiled: May 1, 2018Date of Patent: May 25, 2021Assignee: Qualcomm IncorporatedInventors: Kuljit Singh Bains, Raj Ramanujan, Liyong Wang, Wesley Queen
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Patent number: 10996888Abstract: Systems and methods for synchronizing write credits between a host device and a media controller of a memory system comprising a non-volatile memory (NVM), wherein the host device is configured to maintain a write credit (WC) counter implemented in a memory controller of the host device. The WC counter tracks and limits the number of outstanding write commands which may be issued to the NVM. The host device may query the memory system to obtain status of the available write buffer space in the media controller, and adjust the WC counter based on any detected errors in the write buffer space reported in metadata of read packets sent from the memory system.Type: GrantFiled: October 30, 2018Date of Patent: May 4, 2021Assignee: Qualcomm IncorporatedInventors: Kuljit Singh Bains, Raj Ramanujan, Wesley Queen, Liyong Wang
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Publication number: 20210051096Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.Type: ApplicationFiled: October 30, 2020Publication date: February 18, 2021Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj Ramanujan, Brian Slechta
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Publication number: 20190339865Abstract: In non-energy-backed memory with persistent storage, a complex protocol is required to handle persistent writes. To address this issue, it is proposed to provide a simple protocol to handle persistent writes in energy-backed memory with persistent storage.Type: ApplicationFiled: May 1, 2018Publication date: November 7, 2019Inventors: Kuljit Singh BAINS, Raj RAMANUJAN, Liyong WANG, Wesley QUEEN
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Patent number: 10359940Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.Type: GrantFiled: November 7, 2017Date of Patent: July 23, 2019Assignee: Intel CorporationInventors: Mark A. Schmisseur, Mohan J. Kumar, Balint Fleischer, Debendra Das Sharma, Raj Ramanujan
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Publication number: 20190129656Abstract: Systems and methods for synchronizing write credits between a host device and a media controller of a memory system comprising a non-volatile memory (NVM), wherein the host device is configured to maintain a write credit (WC) counter implemented in a memory controller of the host device. The WC counter tracks and limits the number of outstanding write commands which may be issued to the NVM. The host device may query the memory system to obtain status of the available write buffer space in the media controller, and adjust the WC counter based on any detected errors in the write buffer space reported in metadata of read packets sent from the memory system.Type: ApplicationFiled: October 30, 2018Publication date: May 2, 2019Inventors: Kuljit Singh BAINS, Raj RAMANUJAN, Wesley QUEEN, Liyong WANG
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Publication number: 20190087096Abstract: Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Inventors: Raj RAMANUJAN, Kuljit Singh BAINS, Liyong WANG, Wesley QUEEN
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Publication number: 20180157424Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.Type: ApplicationFiled: November 7, 2017Publication date: June 7, 2018Inventors: Mark A. SCHMISSEUR, Mohan J. KUMAR, Balint FLEISCHER, Debendra DAS SHARMA, Raj Ramanujan
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Patent number: 8838935Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.Type: GrantFiled: September 24, 2010Date of Patent: September 16, 2014Assignee: Intel CorporationInventors: Glenn Hinton, Madhavan Parthasarathy, Rajesh Parthasarathy, Muthukumar Swaminathan, Raj Ramanujan, David Zimmerman, Larry O. Smith, Adrian C. Moga, Scott J. Cape, Wayne A. Downer, Robert S. Chappell