Abstract: A system and a method are disclosed for verifying the implementation of a computer chip design. A design including one or more interpretive computer programing language modules and one or more hardware description language (HDL) modules is received. When one of the interpretive programing language modules requests to communicate with one of the HDL modules, the HDL module is enabled and the input arguments from the interpretive programing language module are pipelined into the HDL module. Pipelined output data is received from the HDL module. The received output data is formatted and returned to the interpretive programing language module.

Abstract: A system and a method are disclosed for verifying the implementation of a computer chip design. A design including one or more interpretive computer programing language modules and one or more hardware description language (HDL) modules is received. When one of the interpretive programing language modules requests to communicate with one of the HDL modules, the HDL module is enabled and the input arguments from the interpretive programing language module are pipelined into the HDL module. Pipelined output data is received from the HDL module. The received output data is formatted and returned to the interpretive programing language module.

Abstract: This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation of the high-level language specification into assertion code from these patterns and temporal properties for design verification. This eliminates the need to code extra RTL to handle features such as pipelines and bus priorities. Such common features are specified only in high-level patterns and temporal properties to be verified. This is advantageous because less verification code to be written, automated synthesis of assertions enforces monitor-style of writing assertions rather than generator-style, and the high-level code can be seamlessly migrated to another verification tool by producing another code generator for the new assertion language.