Patents by Inventor Raja Koduri
Raja Koduri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11100004Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.Type: GrantFiled: June 23, 2015Date of Patent: August 24, 2021Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Gongxian Jeffrey Cheng, Mark Fowler, Philip J. Rogers, Benjamin T. Sander, Anthony Asaro, Mike Mantor, Raja Koduri
-
Publication number: 20160378674Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.Type: ApplicationFiled: June 23, 2015Publication date: December 29, 2016Inventors: Gongxian Jeffrey Cheng, Mark Fowler, Philip J. Rogers, Benjamin T. Sander, Anthony Asaro, Mike Mantor, Raja Koduri
-
Patent number: 9299125Abstract: Embodiments are described for a method for using anti-aliasing hardware to generate a higher resolution image at the processing of a lower resolution image with anti-aliasing. A graphics image comprising allocating a buffer used in a multisample anti-aliasing process, wherein the allocated buffer has a dimension comprising a reduction in at least one of the width or height of an original dimension of an original buffer provided by the anti-aliasing hardware; rendering sampled image data to the allocated buffer at a sampling rate proportional to the reduction; and expanding the allocated buffer back to the dimension of the original buffer.Type: GrantFiled: May 3, 2013Date of Patent: March 29, 2016Assignee: Advanced Micro Devices Inc.Inventors: Andrew S Pomianowski, Raja Koduri, Jason Yang, Angus M Dorbie
-
Publication number: 20140327696Abstract: Embodiments are described for a method for using anti-aliasing hardware to generate a higher resolution image at the processing of a lower resolution image with anti-aliasing. A graphics image comprising allocating a buffer used in a multisample anti-aliasing process, wherein the allocated buffer has a dimension comprising a reduction in at least one of the width or height of an original dimension of an original buffer provided by the anti-aliasing hardware; rendering sampled image data to the allocated buffer at a sampling rate proportional to the reduction; and expanding the allocated buffer back to the dimension of the original buffer.Type: ApplicationFiled: May 3, 2013Publication date: November 6, 2014Applicant: Advanced Micro Devices Inc.Inventors: Andrew S. Pomianowski, Raja Koduri, Jason Yang, Angus M. Dorbie
-
Patent number: 8811737Abstract: Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.Type: GrantFiled: July 30, 2013Date of Patent: August 19, 2014Assignee: ATI Technologies ULCInventors: Konstantine Iourcha, Andrew S. C. Pomianowski, Raja Koduri
-
Patent number: 8781260Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.Type: GrantFiled: April 24, 2013Date of Patent: July 15, 2014Assignee: ATI Technologies ULCInventors: James Hunkins, Raja Koduri
-
Publication number: 20130315481Abstract: Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.Type: ApplicationFiled: July 30, 2013Publication date: November 28, 2013Applicant: ATI TECHNOLOGIES ULCInventors: Konstantine Iourcha, Andrew S.C. Pomianowski, Raja Koduri
-
Patent number: 8535086Abstract: In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi-connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts.Type: GrantFiled: February 23, 2012Date of Patent: September 17, 2013Assignee: ATI Technologies ULCInventors: James D. Hunkins, Lawrence J. King, Raja Koduri, III
-
Publication number: 20130235077Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.Type: ApplicationFiled: April 24, 2013Publication date: September 12, 2013Applicant: ATI TECHNOLOGIES ULCInventors: James HUNKINS, Raja KODURI
-
Patent number: 8520943Abstract: Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.Type: GrantFiled: September 16, 2011Date of Patent: August 27, 2013Assignee: ATI Technologies ULCInventors: Konstantine Iourcha, Andrew S. C. Pomianowski, Raja Koduri
-
Patent number: 8514233Abstract: Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc.Type: GrantFiled: January 23, 2009Date of Patent: August 20, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Dmitry Semiannikov, Korhan Erenben, Raja Koduri
-
Patent number: 8452128Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.Type: GrantFiled: January 23, 2012Date of Patent: May 28, 2013Assignee: ATI Technologies ULCInventors: James Hunkins, Raja Koduri
-
Patent number: 8326053Abstract: A method and apparatus provides for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.Type: GrantFiled: June 16, 2009Date of Patent: December 4, 2012Assignee: ATI Technologies ULCInventors: Konstantine Iourcha, Andrew S. C. Pomianowski, Raja Koduri
-
Publication number: 20120274655Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.Type: ApplicationFiled: July 2, 2012Publication date: November 1, 2012Applicant: ATI Technologies, Inc.Inventors: Arcot J. PREETHAM, Andrew S. POMIANOWSKI, Raja KODURI
-
Patent number: 8270476Abstract: Embodiments include a codec for use in a videoconferencing or similar system includes a video encoder pipeline that has a pre-processor component that is optimized to detect faces and compress the facial video data in an optimum manner. The codec has a pre-processing step that analyzes each frame on a per macroblock basis to determine the mathematical activity level per block. The activity level calculation is used as a parameter to the bitrate control module of the encoder to control the quantization, and thus the fine grained quality of the output data. An object detection module (e.g., a face detector) is placed in the pre-processing step. The object detection data is then combined with the activity level and object detection certainty value through a combinatorial algorithm comprising a weighted average or normalized multiplication process.Type: GrantFiled: December 31, 2008Date of Patent: September 18, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Michael L. Schmit, Raja Koduri, Carrell Ray Killebrew
-
Publication number: 20120221758Abstract: In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi- connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts.Type: ApplicationFiled: February 23, 2012Publication date: August 30, 2012Applicant: ATI TECHNOLOGIES ULCInventors: James D. Hunkins, Lawrence J. King, Raja Koduri
-
Patent number: 8212838Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.Type: GrantFiled: May 27, 2005Date of Patent: July 3, 2012Assignee: ATI Technologies, Inc.Inventors: Arcot J. Preetham, Andrew S. Pomianowski, Raja Koduri
-
Patent number: 8199164Abstract: A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.Type: GrantFiled: September 22, 2009Date of Patent: June 12, 2012Assignee: ATI Technologies ULCInventors: Raja Koduri, Gordon M. Elder, Jeffrey A. Golds
-
Publication number: 20120120079Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.Type: ApplicationFiled: January 23, 2012Publication date: May 17, 2012Applicant: ATI TECHNOLOGIES, INC.Inventors: James Hunkins, Raja Koduri
-
Patent number: 8137127Abstract: In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi-connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts. In one example, the electronic device housing includes air flow passages, such as grills, adapted to provide air flow through the housing.Type: GrantFiled: December 13, 2007Date of Patent: March 20, 2012Assignee: ATI Technologies ULCInventors: James D. Hunkins, Lawrence J. King, Raja Koduri