Abstract: A high-speed maximum likelihood sequence estimation method and device. The method includes identifying candidate paths through a state trellis based on a group of observed data, where each candidate path corresponds to a best path through a trellis beginning at one of a possible prior states (and corresponding prior data bit or bits), and then selecting one of the paths based on candidate sequence selection information, typically prior state decisions (e.g., data symbols in the form of one or more bits). The path selection, in turn, provides decoding of symbols and data bit information for use in selecting one of the candidate paths in a subsequent stage.

Abstract: A high-speed maximum likelihood sequence estimation method and device. The method includes identifying candidate paths through a state trellis based on a group of observed data, where each candidate path corresponds to a best path through a trellis beginning at one of a possible prior states (and corresponding prior data bit or bits), and then selecting one of the paths based on candidate sequence selection information, typically prior state decisions (e.g., data symbols in the form of one or more bits). The path selection, in turn, provides decoding of symbols and data bit information for use in selecting one of the candidate paths in a subsequent stage.

Abstract: A high-speed maximum likelihood sequence estimation method and device. The method includes identifying candidate paths through a state trellis based on a group of observed data, where each candidate path corresponds to a best path through a trellis beginning at one of a possible prior states (and corresponding prior data bit or bits), and then selecting one of the paths based on candidate sequence selection information, typically prior state decisions (e.g., data symbols in the form of one or more bits). The path selection, in turn, provides decoding of symbols and data bit information for use in selecting one of the candidate paths in a subsequent stage.

Abstract: A high-speed maximum likelihood sequence estimation method and device. The method includes identifying candidate paths through a state trellis based on a group of observed data, where each candidate path corresponds to a best path through a trellis beginning at one of a possible prior states (and corresponding prior data bit or bits), and then selecting one of the paths based on candidate sequence selection information, typically prior state decisions (e.g., data symbols in the form of one or more bits). The path selection, in turn, provides decoding of symbols and data bit information for use in selecting one of the candidate paths in a subsequent stage.

Abstract: The invention involves a die having domino circuits. In some embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and at least one intermediate node. The domino stage has improved noise immunity and reduced leakage through reverse body biasing transistors in the evaluate network by raising voltage of the at least one intermediate node without static power consumption through the evaluate network. In other embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and wherein the domino stage further includes a diode transistor having a gate and an additional terminal connected to the domino stage output node.

Abstract: The invention involves a die having domino circuits. In some embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and at least one intermediate node. The domino stage has improved noise immunity and reduced leakage through reverse body biasing transistors in the evaluate network by raising voltage of the at least one intermediate node without static power consumption through the evaluate network. In other embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and wherein the domino stage further includes a diode transistor having a gate and an additional terminal connected to the domino stage output node.

Abstract: The invention involves a die having domino circuits. In some embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and at least one intermediate node. The domino stage has improved noise immunity and reduced leakage through reverse body biasing transistors in the evaluate network by raising voltage of the at least one intermediate node without static power consumption through the evaluate network. In other embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and wherein the domino stage further includes a diode transistor having a gate and an additional terminal connected to the domino stage output node.