Abstract: Electrostatic discharge (ESD) protection for circuits which utilize multiple power supply rails, both positive (Vdd) and negative (Vss). Vdd busses remain completely isolated, while Vss busses are joined by pairs of complementary polarity diodes (made typically with P+/N-well diodes in an N/P-substrate process) thus keeping Vss busses isolated from each other. The I/O diodes of high frequency I/O pads are arranged in a square layout to achieve the best current/capacitance ratio. Each pair of power rails is provided with its own power shunt circuit, placing each shunt in physical proximity to the I/O pad it must protect. Shunts are designed to clamp at a very low voltage during an ESD event using mostly PMOS transistors. The protection circuit is laid out such that the worst case ESD event will flow at most between two I/O pads and one power shunt.

Abstract: Electrostatic discharge (ESD) protection for circuits which utilize multiple power supply rails, both positive (Vdd) and negative (Vss). Vdd busses remain completely isolated, while Vss busses are joined by pairs of complementary polarity diodes (made typically with P+/N-well diodes in an N/P-substrate process) thus keeping Vss busses isolated from each other. The I/O diodes of high frequency I/O pads are arranged in a square layout to achieve the best current/capacitance ratio. Each pair of power rails is provided with its own power shunt circuit, placing each shunt in physical proximity to the I/O pad it must protect. Shunts are designed to clamp at a very low voltage during an ESD event using mostly PMOS transistors. The protection circuit is laid out such that the worst case ESD event will flow at most between two I/O pads and one power shunt.

Abstract: Method and apparatus for low-power charge transition in an I/O system of an integrated circuit comprising an interconnected linking of stepwise charging and charge recycling of capacitive loads. The I/O system according to the invention does not need additional pins for recycling capacitors, additional silicon area for on-chip capacitors, or additional power supplies. This I/O system achieves power savings of 20% to 30% of CV.sup.2 f.

Abstract: A predriver circuit for current switching, di/dt, noise control for high current load devices is disclosed. Parallel weak pull up and pull down circuit paths are combined with strong pull up and pull down circuit paths, respectively, to provide control over the rate of change of current through the load during predetermined turn-on and turn-off time periods. Predriver control for both NMOS driver, current sink NMOS, and PMOS driver, current source PMOS, are demonstrated. The predriver circuit provides control of the rate of current switching through the load without excessive delay in fully turning on or off the load device.