Patents by Inventor Rajarshi Mukhopadhyay
Rajarshi Mukhopadhyay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11709186Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.Type: GrantFiled: April 16, 2021Date of Patent: July 25, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
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Publication number: 20230028897Abstract: Disclosed is a system and method for validating and correcting sync errors of captions of a media asset comprising a caption file, wherein each caption has a start time and an end time. The system decodes the caption file using caption decoder for generating a format agnostic XML file, a transcriber engine extracts an audio track and transcribes the audio for generating a transcript, a caption analyser identifies matching set of words in the transcript and assign a match score and classifies the captions as one of MATCHING and UNDETECTED based on the match score. The caption analyser determines sync offset for each caption that is classified as MATCHNING and the system uses a prediction engine for predicting sync offset of the captions that are classified as UNDETECTED.Type: ApplicationFiled: November 29, 2021Publication date: January 26, 2023Applicant: VENERA TECHNOLOGIES INC.Inventor: Rajarshi MUKHOPADHYAY
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Patent number: 11538771Abstract: In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.Type: GrantFiled: August 4, 2020Date of Patent: December 27, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Barry Jon Male, Rajarshi Mukhopadhyay
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Patent number: 11417725Abstract: An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.Type: GrantFiled: November 25, 2020Date of Patent: August 16, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dan Carothers, Ricky Jackson, Rajarshi Mukhopadhyay, Ben Cook
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Patent number: 11218072Abstract: Modulating a gate drive current supplied to an output drive switch coupled to an electric motor by performing at least the following: obtain a gate drive current modulation profile, supply, based on the gate drive current modulation profile, a first gate drive current level as the gate drive current when the output drive switch is operating within a first region, drop the first gate drive current level to a second gate drive current level when the output drive switch transitions from the first region to operating within a Miller region, increase the second gate drive current level to a third gate drive current level within the Miller region, and set the gate drive current to a fourth gate drive current level when the output drive switch transitions from the Miller region to operating within a third region.Type: GrantFiled: July 2, 2019Date of Patent: January 4, 2022Assignee: Texas Instruments IncorporatedInventors: Rajarshi Mukhopadhyay, Sooping Saw, Anuj Jain
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Publication number: 20210231712Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.Type: ApplicationFiled: April 16, 2021Publication date: July 29, 2021Inventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
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Patent number: 11075627Abstract: Methods and circuitry for driving a device are disclosed. An example of the circuitry includes a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider, and a current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor.Type: GrantFiled: July 6, 2020Date of Patent: July 27, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
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Patent number: 11070197Abstract: Methods, apparatus, systems and articles of manufacture are described for transistor health monitoring. An example gate driver includes a request receiver pin, a measurement transmitter pin, and a driver control logic pin, the request receiver pin, the measurement transmitter pin, and the driver control logic pin configured to be coupled to a controller, a sensing pin, the sensing pin to be coupled to a sensing circuit, a control logic circuit having an input coupled to the request receiver pin, a transistor coupled to the control logic circuit and the sensing pin, a multiplexer coupled to the control logic circuit and the sensing pin, an analog-to-digital converter (ADC) coupled to the multiplexer and the measurement transmitter pin, and a driver control logic circuit coupled to the driver control logic pin.Type: GrantFiled: December 31, 2019Date of Patent: July 20, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gangyao Wang, Rajarshi Mukhopadhyay, Miguel Aguirre
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Publication number: 20210203309Abstract: Methods, apparatus, systems and articles of manufacture are described for transistor health monitoring. An example gate driver includes a request receiver pin, a measurement transmitter pin, and a driver control logic pin, the request receiver pin, the measurement transmitter pin, and the driver control logic pin configured to be coupled to a controller, a sensing pin, the sensing pin to be coupled to a sensing circuit, a control logic circuit having an input coupled to the request receiver pin, a transistor coupled to the control logic circuit and the sensing pin, a multiplexer coupled to the control logic circuit and the sensing pin, an analog-to-digital converter (ADC) coupled to the multiplexer and the measurement transmitter pin, and a driver control logic circuit coupled to the driver control logic pin.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Inventors: Gangyao Wang, Rajarshi Mukhopadhyay, Miguel Aguirre
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Patent number: 11050420Abstract: In described examples, bootstrap diode circuits include a first diode having a first diode input coupled to a voltage supply and a first diode output. Described bootstrap diode circuits additionally include a second diode having a second diode input coupled to the first diode output and a second diode output and a plurality of zener diodes coupled in series. The series-coupled zener diodes are further coupled in parallel with the second diode.Type: GrantFiled: January 24, 2018Date of Patent: June 29, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajarshi Mukhopadhyay, Nathan Schemm, Xiaonan Wang
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Patent number: 11009530Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.Type: GrantFiled: February 21, 2020Date of Patent: May 18, 2021Assignee: Texas Instruments IncorporatedInventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
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Patent number: 11002563Abstract: A first amplifier has an input to receive a Hall-signal output current from a first Hall element and has an output to output feedback current in response to the received Hall-signal output current. The Hall-signal output current is impeded by an impedance of the first Hall element. The feedback current is coupled to counterpoise the Hall-signal output current at the input, and a voltage at the output is an amplified Hall output signal. A second amplifier generates a high-frequency portion output signal in response to a difference between the amplified Hall output signal and a Hall-signal output signal from a second Hall element. A filter reduces high-frequency content of the high-frequency portion output signal and generates an offset correction signal. A third amplifier generates a corrected Hall signal in response to a difference between the amplified Hall output signal and the offset correction signal.Type: GrantFiled: April 9, 2020Date of Patent: May 11, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Arup Polley, Srinath Ramaswamy, Baher S. Haroun, Rajarshi Mukhopadhyay
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Publication number: 20210083047Abstract: An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.Type: ApplicationFiled: November 25, 2020Publication date: March 18, 2021Inventors: Dan Carothers, Ricky Jackson, Rajarshi Mukhopadhyay, Ben Cook
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Patent number: 10854712Abstract: An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.Type: GrantFiled: February 4, 2019Date of Patent: December 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dan Carothers, Ricky Jackson, Rajarshi Mukhopadhyay, Ben Cook
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Publication number: 20200365532Abstract: In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.Type: ApplicationFiled: August 4, 2020Publication date: November 19, 2020Inventors: Barry Jon Male, Rajarshi Mukhopadhyay
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Publication number: 20200336142Abstract: Methods and circuitry for driving a device are disclosed. An example of the circuitry includes a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider, and a current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor.Type: ApplicationFiled: July 6, 2020Publication date: October 22, 2020Inventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
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Patent number: 10742134Abstract: A method and device for providing isolated power transfer to a low-power load across a capacitor of a series resonance circuit are shown. The method includes comparing an output voltage received via a feedback loop with a desired output voltage. Responsive to determining that the output voltage is not equal to the desired output voltage, the method determines a sub-harmonic order of the resonant frequency of the series resonance circuit to use as a switching frequency and switches the series resonance circuit at substantially the determined subharmonic order of the resonant frequency.Type: GrantFiled: August 24, 2017Date of Patent: August 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lei Chen, Rajarshi Mukhopadhyay, Mark W. Morgan, Joseph A. Sankman
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Patent number: 10742209Abstract: Methods and circuitry for driving a device are disclosed. An example of the circuitry includes a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider, and a current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor.Type: GrantFiled: February 12, 2019Date of Patent: August 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Olivier Trescases, Johan Tjeerd Strydom, Rajarshi Mukhopadhyay
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Patent number: 10734331Abstract: In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.Type: GrantFiled: August 16, 2017Date of Patent: August 4, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Barry Jon Male, Rajarshi Mukhopadhyay
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Publication number: 20200240811Abstract: A first amplifier has an input to receive a Hall-signal output current from a first Hall element and has an output to output feedback current in response to the received Hall-signal output current. The Hall-signal output current is impeded by an impedance of the first Hall element. The feedback current is coupled to counterpoise the Hall-signal output current at the input, and a voltage at the output is an amplified Hall output signal. A second amplifier generates a high-frequency portion output signal in response to a difference between the amplified Hall output signal and a Hall-signal output signal from a second Hall element. A filter reduces high-frequency content of the high-frequency portion output signal and generates an offset correction signal. A third amplifier generates a corrected Hall signal in response to a difference between the amplified Hall output signal and the offset correction signal.Type: ApplicationFiled: April 9, 2020Publication date: July 30, 2020Inventors: Arup Polley, Srinath Ramaswamy, Baher S. Haroun, Rajarshi Mukhopadhyay