Patents by Inventor Rajat Agarwal

Rajat Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11567877
    Abstract: An embodiment of a memory controller device includes technology to control access to a multi-level memory including at least a first level memory and a second level memory, provide direct access to the first level memory based on a system memory address, cache accesses to the second level memory in a second portion of the first level memory, and address a memory space with a total memory capacity which includes a first capacity of the first portion of the first level memory plus a second capacity of the second level memory. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 31, 2023
    Assignee: Intel Corporation
    Inventors: Suresh S. Chittor, Rajat Agarwal, Wei P. Chen
  • Patent number: 11557541
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala
  • Publication number: 20220365885
    Abstract: Techniques are described for providing low-overhead cryptographic memory isolation to mitigate attack vulnerabilities in a multi-user virtualized computing environment. Memory read and memory write operations for target data, each operation initiated via an instruction associated with a particular virtual machine (VM), include the generation and/or validation of a message authentication code that is based at least on a VM-specific cryptographic key and a physical memory address of the target data. Such operations may further include transmitting the generated message authentication code via a plurality of ancillary bits incorporated within a data line that includes the target data. In the event of a validation failure, one or more error codes may be generated and provided to distinct trust domain architecture entities based on an operating mode of the associated virtual machine.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Applicant: Intel Corporation
    Inventors: Siddhartha Chhabra, Rajat Agarwal, Baiju Patel, Kirk Yap
  • Publication number: 20220350500
    Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 3, 2022
    Inventors: Wei P. CHEN, Theodros YIGZAW, Sarathy JAYAKUMAR, Anthony LUCK, Deep K. BUCH, Rajat AGARWAL, Kuljit S. BAINS, John G. HOLM, Brent CHARTRAND, Keith KLAYMAN
  • Publication number: 20220308998
    Abstract: An apparatus and method to reduce bandwidth and latency associated with probabilistic caches.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Ruchira SASANKA, Rajat AGARWAL
  • Patent number: 11397692
    Abstract: Techniques are described for providing low-overhead cryptographic memory isolation to mitigate attack vulnerabilities in a multi-user virtualized computing environment. Memory read and memory write operations for target data, each operation initiated via an instruction associated with a particular virtual machine (VM), include the generation and/or validation of a message authentication code that is based at least on a VM-specific cryptographic key and a physical memory address of the target data. Such operations may further include transmitting the generated message authentication code via a plurality of ancillary bits incorporated within a data line that includes the target data. In the event of a validation failure, one or more error codes may be generated and provided to distinct trust domain architecture entities based on an operating mode of the associated virtual machine.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Rajat Agarwal, Baiju Patel, Kirk Yap
  • Publication number: 20220229724
    Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Inventors: Kuljit S. BAINS, Rajat AGARWAL, Jongwon LEE
  • Publication number: 20220229575
    Abstract: A system can dynamically migrate memory pages from near memory to far memory during runtime. A system basic input output system (BIOS) can program a first memory address space of size P and a second memory address space of size P to a near memory (NM) space of size (N) and a far memory (FM) space of size (M), where P equals N+M. For the first memory address space, the OS can manage the NM space and the FM space as a flat memory space with an address space of size P available. For the second memory address space, the OS can manage the NM space as a NM cache for FM, with an address space of size M available.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 21, 2022
    Inventors: Wei P. CHEN, Andrew M. RUDOFF, Rajat AGARWAL
  • Publication number: 20220222178
    Abstract: A system includes a multilevel memory such as a two level memory (2LM), where a first level memory acts as a cache for the second level memory. A memory controller or cache controller can detect a cache miss in the first level memory for a request for data. Instead of automatically performing a swap, the controller can determine whether to perform a swap based on a swap policy assigned to a memory region associated with the address of the requested data.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Inventors: Rajat AGARWAL, Sai Prashanth MURALIDHARA, Wei P. CHEN, Nishant SINGH, Sharada VENKATESWARAN, Daniel W. LIU
  • Publication number: 20220207190
    Abstract: Techniques for Scalable Memory Integrity and Enhanced Reliability, Availability, and Serviceability (SMIRAS) based systems are described. A SMIRAS based system may be enabled to use an integrity-based metadata organization that stores data, metadata, and a first portion of ECC data together in memory and a second portion of ECC data in sequestered memory; or using a compression based organization that stores compressed data, compression metadata, and an second portion of ECC data as a cacheline.
    Type: Application
    Filed: December 26, 2020
    Publication date: June 30, 2022
    Inventors: Siddhartha CHHABRA, Manjula PEDDIREDDY, Rajat AGARWAL
  • Patent number: 11314589
    Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, Rajat Agarwal, Jongwon Lee
  • Publication number: 20220114112
    Abstract: A method comprises generating, for a cacheline, a first tag and a second tag, the first tag and the second tag generated as a function of user data stored and metadata in the cacheline stored in a first memory device, and a multiplication parameter derived from a secret key, storing the user data, the metadata, the first tag and the second tag in the first cacheline of the first memory device; generating, for the cacheline, a third tag and a fourth tag, the third tag and the fourth tag generated as a function of the user data stored and metadata in the cacheline stored in a second memory device, and the multiplication parameter; storing the user data, the metadata, the third tag and the fourth tag in the corresponding cache line of the second memory device; receiving, from a requesting device, a read operation directed to the cacheline; and using the first tag, the second tag, the third tag, and the fourth tag to determine whether a read error occurred during the read operation.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: Intel Corporation
    Inventors: Sergej Deutsch, Karanvir Grewal, David M. Durham, Rajat Agarwal
  • Publication number: 20220107866
    Abstract: A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow. The read data is stored in a read data buffer at the memory controller when the read data is received from memory. Once the ECC circuitry detects an error in the read data, the retry flow enables access to that data from the read data buffer instead of reading the data from memory for the second time. Access to the data from the read data buffer reduces the overall time needed for the correction flow compared to a retry flow that rereads the data from memory.
    Type: Application
    Filed: December 14, 2021
    Publication date: April 7, 2022
    Inventors: Jing LING, Wei P. CHEN, Rajat AGARWAL
  • Publication number: 20220094553
    Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: David M. Durham, Rajat Agarwal, Siddhartha Chhabra, Sergej Deutsch, Karanvir S. Grewal, Ioannis T. Schoinas
  • Publication number: 20220083950
    Abstract: A skilled service marketplace scheduling system and method is provided. The system can include a skilled service marketplace coordination system, one or more skilled service marketplace requester devices, and one or more skilled service marketplace provider devices. The coordination system may determine a schedule given a skilled service marketplace request and a skilled service marketplace provider schedule. The coordination system may assign a given request to a skilled service provider based on the skill level of the skilled service provider. The coordination system can account for travel time between the requester and the skilled service provider. The system may interact with third party systems, such as a parts inventory, to create the skilled service marketplace schedule. The system can confirm adequate performance of the skilled service.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 17, 2022
    Inventors: Rajat Agarwal, Xue Han
  • Patent number: 11196565
    Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: December 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: David M. Durham, Rajat Agarwal, Siddhartha Chhabra, Sergej Deutsch, Karanvir S. Grewal, Ioannis T. Schoinas
  • Publication number: 20210336767
    Abstract: A memory subsystem includes link encryption for the system memory data bus. The memory controller can provide encryption for data at rest and link protection. The memory controller can optionally provide link encryption. Thus, the system can provide link protection for the data in transit. The memory module can include a link decryption engine that can decrypt link encryption if it is used, and performs a link integrity check with a link integrity tag associated with the link protection. The memory devices can then store the encrypted protected data and ECC data from the link decryption engine after link protection verification.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 28, 2021
    Inventors: Raghunandan MAKARAM, Kirk S. YAP, Rajat AGARWAL, George VERGIS, Bill NALE, Jacob DOWECK
  • Patent number: 11132298
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Glenn J Hinton
  • Publication number: 20210263855
    Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.
    Type: Application
    Filed: April 6, 2021
    Publication date: August 26, 2021
    Inventors: Andy Rudoff, Tiffany J. Kasanicky, Wei P. Chen, Rajat Agarwal, Chet R. Douglas
  • Patent number: 11088846
    Abstract: In one example a computer implemented method comprises encrypting data to be stored in a protected region of a memory using a message authentication code (MAC) having a first value determined using a first key during a first period of time, generating a replay integrity tree structure comprising security metadata for the data stored in the protected region of the memory using the first value of the MAC, and at the end of the first period of time, re-keying the MAC to have a second value determined using a second key at the end of the first period of time, decrypting the data stored in the protected region using the first value for the MAC, re-encrypting the data stored in the protected region using the second value for the MAC, and updating the replay integrity tree using the second value for the MAC. Other examples may be described.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 10, 2021
    Assignee: INTEL CORPORATION
    Inventors: Siddhartha Chhabra, Rajat Agarwal, David M. Durham