Patents by Inventor Rajat Arora

Rajat Arora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230368140
    Abstract: In some implementations, supporting system collaboration includes actions of receiving a registration of an account on a system, adding objects to an object list including model information that includes an identifier of a physical object and characteristics of the physical object, publishing the object list to make the object list visible to a plurality of users of the first system, receiving, from one of the plurality of users of the system, a request to export a portion of the object list, conditioning the portion of the object list to be accessible to another system by converting the portion of the object list based on a transmission protocol, formatting the portion of the object list for display on the other system, and packaging the portion of the object list for transmission to the other system, and exporting the portion of the object list to the other system.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Inventors: Rajarshi Ghosh, Simone Turrin, Petra Eder, Ranjith Kumar Nookala, Rajat Arora, Tzanko Stefanov
  • Publication number: 20230368142
    Abstract: In some implementations, supporting system collaboration includes actions of generating a digital identifier for a digital object corresponding to a physical object included in an object list formatted for display and including model information retrieved from a second system coupled to the first system, the model information including an identifier of a physical object and one or more characteristics of the physical object, assigning the digital identifier of the digital object to a service to be performed on the physical object, transmitting, to a second system, the digital identifier, the second system performing a service related to the physical object, receiving, to a second system, a service result related to the physical object, and transmitting, to a third system, the service result related to the physical object.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Inventors: Rajarshi Ghosh, Simone Turrin, Petra Eder, Ranjith Kumar Nookala, Rajat Arora, Tzanko Stefanov
  • Patent number: 10977441
    Abstract: Techniques for routing items addressed to an unstructured address are described. One embodiment includes receiving an order for delivery of a first package, the order specifying a first address that does not comply with a defined address format. The first address is processed using one or more hybrid machine learning algorithms to determine a Normalized Delivery Location (NDL) associated with the first address. A sorting zone that encompasses the NDL is determined. The sorting zones correspond to a predefined geographic region. Embodiments facilitate transport of the first package to a physical shipping location within the predefined geographic region.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 13, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Alok Tiwari, Rajat Arora, Bonney Varghese, Vamshi Surabhi, Homayoun Taherian, Abhishek Verma
  • Publication number: 20200134014
    Abstract: Techniques for routing items addressed to an unstructured address are described. One embodiment includes receiving an order for delivery of a first package, the order specifying a first address that does not comply with a defined address format. The first address is processed using one or more hybrid machine learning algorithms to determine a Normalized Delivery Location (NDL) associated with the first address. A sorting zone that encompasses the NDL is determined. The sorting zones correspond to a predefined geographic region. Embodiments facilitate transport of the first package to a physical shipping location within the predefined geographic region.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: Alok TIWARI, Rajat ARORA, Bonney VARGHESE, Vamshi SURABHI, Homayoun TAHERIAN, Abhishek VERMA
  • Patent number: 10041026
    Abstract: The present invention relates to a multi-compartment water soluble laundry detergent capsule formed from water-soluble polyvinyl alcohol film and a method of preparing a component of the capsule wherein the capsule comprises: i) a first compartment for holding solid material comprising HEDP sequestrant or a salt thereof; and ii) a second compartment for holding liquid material comprising an aqueous liquid laundry detergent comprising: surfactant, enzymes and hydrotrope wherein: a) the HEDP is present in the capsule in the form of loose packed granules and comprises at least 25% by weight of the solid material in the first compartment; and b) wherein the HEDP further comprises 1.5% by weight or less of fines particles with a particle of less than 180 microns and 3.0% by weight or less of fines particles with a particle size of less than 355 microns.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: August 7, 2018
    Assignee: Conopco, Inc.
    Inventors: Rajat Arora, Mark John Henry, Kerry Elizabeth Hodkinson
  • Publication number: 20170067004
    Abstract: The present invention relates to a multi-compartment water soluble laundry detergent capsule formed from water-soluble polyvinyl alcohol film and a method of preparing a component of the capsule wherein the capsule comprises: i) a first compartment for holding solid material comprising HEDP sequestrant or a salt thereof; and ii) a second compartment for holding liquid material comprising an aqueous liquid laundry detergent comprising: surfactant, enzymes and hydrotrope wherein: a) the HEDP is present in the capsule in the form of loose packed granules and comprises at least 25% by weight of the solid material in the first compartment; and b) wherein the HEDP further comprises 1.5% by weight or less of fines particles with a particle of less than 180 microns and 3.0% by weight or less of fines particles with a particle size of less than 355 microns.
    Type: Application
    Filed: February 17, 2015
    Publication date: March 9, 2017
    Applicant: Conopco, Inc., d/b/a UNILEVER
    Inventors: Rajat ARORA, Mark John HENRY, Kerry Elizabeth HODKINSON
  • Patent number: 7669165
    Abstract: Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: February 23, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Rajat Arora, Chih-Chang Lin, Huan-Chih Tsai, Bharat Chandramouli, Kei-Yong Khoo
  • Publication number: 20080127014
    Abstract: Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.
    Type: Application
    Filed: October 25, 2006
    Publication date: May 29, 2008
    Applicant: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Rajat Arora, Chih-Chang Lin, Huan-Chih Tsai, Bharat Chandramouli, Kei-Yong Khoo