Patents by Inventor Rajay R. Pai

Rajay R. Pai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements
    Patent number: 6477674
    Abstract: In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circuit is operating in a loopback test mode. According to a further embodiment, the integrated circuit includes one or more programmable delay circuits coupled to the I/O buffers that permit switching state (AC) loopback timing tests to be conducted.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: November 5, 2002
    Assignee: Intel Corporation
    Inventors: Sarah E. Bates, R. Tim Frodsham, Nasser A. Kurd, Anne Meixner, David J. O'Brien, Rajay R. Pai, Mike Tripp, Jeff Wight