Patents by Inventor Rajdeep Mukhopadhyay
Rajdeep Mukhopadhyay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848552Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: GrantFiled: May 6, 2022Date of Patent: December 19, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Patent number: 11837999Abstract: An audio amplifier employs an idle mode to reduce power consumption and improve efficiency of the amplifier. The audio amplifier comprises a modulator configured to receive an analog input signal. The modulator is operable to convert the analog input signal to differential first and second quantized signals, each having a common mode duty cycle. The modulator causes the common mode duty cycle of each of the first and second quantized signals to be shifted when the level of the analog input signal is below a threshold level so that the common mode duty cycle is one of greater than or less than fifty percent (50%). The amplifier further includes a power stage that receives the first and second quantized signals and generates corresponding first and second output signals configured to drive a load, wherein the first and second output signals switched between a supply voltage and a second voltage based on the respective first and second quantized signals.Type: GrantFiled: April 12, 2021Date of Patent: December 5, 2023Assignee: Maxim Integrated Products, Inc.Inventors: Rajdeep Mukhopadhyay, Euan Murphy, Matt Felder, Simon Quinn
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Publication number: 20230216396Abstract: A method for powering driver circuitry for an upper transistor of a half-bridge switching stage includes (1) selectively charging a boot-strap capacitor via a first voltage source such that a voltage at the boot-strap capacitor remains within a predetermined voltage range, (2) clamping the voltage at the boot-strap capacitor to prevent the voltage at the boot-strap capacitor from exceeding a predetermined maximum value, and (3) electrically powering the driver circuitry at least partially via the boot-strap capacitor.Type: ApplicationFiled: December 1, 2022Publication date: July 6, 2023Inventors: Rajdeep Mukhopadhyay, Christopher Francis Edwards
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Publication number: 20220263309Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: ApplicationFiled: May 6, 2022Publication date: August 18, 2022Inventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Patent number: 11355918Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: GrantFiled: October 23, 2020Date of Patent: June 7, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Publication number: 20210367566Abstract: An audio amplifier employs an idle mode to reduce power consumption and improve efficiency of the amplifier. The audio amplifier comprises a modulator configured to receive an analog input signal. The modulator is operable to convert the analog input signal to differential first and second quantized signals, each having a common mode duty cycle. The modulator causes the common mode duty cycle of each of the first and second quantized signals to be shifted when the level of the analog input signal is below a threshold level so that the common mode duty cycle is one of greater than or less than fifty percent (50%). The amplifier further includes a power stage that receives the first and second quantized signals and generates corresponding first and second output signals configured to drive a load, wherein the first and second output signals switched between a supply voltage and a second voltage based on the respective first and second quantized signals.Type: ApplicationFiled: April 12, 2021Publication date: November 25, 2021Inventors: Rajdeep Mukhopadhyay, Euan Murphy, Matt Felder, Simon Quinn
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Patent number: 10951204Abstract: A digital pulse width modulation driver system and method can include: receiving input digital data with a digital signal processing chip on a device; converting the input digital data into pulse width modulated data; generating an amplitude signal with the digital signal processing chip; transmitting the amplitude signal and the pulse width modulated data from a transmit interface within the device to a receive interface within an analog driver chip; and amplifying the pulse width modulated data with a driver coupled to a high voltage rail based on the amplitude signal corresponding to the high voltage rail, or amplifying the pulse width modulated data with the driver coupled to a low voltage rail based on the amplitude signal corresponding to the low voltage rail.Type: GrantFiled: August 28, 2019Date of Patent: March 16, 2021Assignee: Maxim Integrated Products, Inc.Inventors: Simon Kenneth Quinn, Ross William Ballany, Rajdeep Mukhopadhyay, Sergei Slavnov
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Publication number: 20210044101Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Inventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Patent number: 10855069Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: GrantFiled: April 17, 2018Date of Patent: December 1, 2020Assignee: Texas Instruments IncorporatedInventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Publication number: 20200076414Abstract: A digital pulse width modulation driver system and method can include: receiving input digital data with a digital signal processing chip on a device; converting the input digital data into pulse width modulated data; generating an amplitude signal with the digital signal processing chip; transmitting the amplitude signal and the pulse width modulated data from a transmit interface within the device to a receive interface within an analog driver chip; and amplifying the pulse width modulated data with a driver coupled to a high voltage rail based on the amplitude signal corresponding to the high voltage rail, or amplifying the pulse width modulated data with the driver coupled to a low voltage rail based on the amplitude signal corresponding to the low voltage rail.Type: ApplicationFiled: August 28, 2019Publication date: March 5, 2020Applicant: Maxim Integrated Products, Inc.Inventors: Simon Kenneth Quinn, Ross William Ballany, Rajdeep Mukhopadhyay, Sergei Slavnov
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Patent number: 10476266Abstract: A power controller that includes first and second buck controllers and a power balancer. The first buck controller is configured to receive a first power rail at a first voltage and generate a first output signal. The second buck controller is configured to receive a second power rail at a second voltage and generate a second output signal. The power balancer is configured to receive an average current for the output signals and generate, based on the average current, a reference voltage to be received by the second buck controller. The output signals are combined to create a output power rail such that the first buck controller functions as a voltage source for the output power rail and the second buck controller controls, based on the reference voltage, an amount of current in the output power rail received from each of the buck controllers.Type: GrantFiled: March 30, 2015Date of Patent: November 12, 2019Assignee: Texas Instruments IncorporatedInventors: Sanjay Gurlahosur, Rajdeep Mukhopadhyay
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Publication number: 20190319447Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: ApplicationFiled: April 17, 2018Publication date: October 17, 2019Inventors: Rajdeep Mukhopadhyay, PuIkit Shah, Vinod Joseph Menezes
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Publication number: 20150288178Abstract: A power controller that includes first and second buck controllers and a power balancer. The first buck controller is configured to receive a first power rail at a first voltage and generate a first output signal. The second buck controller is configured to receive a second power rail at a second voltage and generate a second output signal. The power balancer is configured to receive an average current for the output signals and generate, based on the average current, a reference voltage to be received by the second buck controller. The output signals are combined to create a output power rail such that the first buck controller functions as a voltage source for the output power rail and the second buck controller controls, based on the reference voltage, an amount of current in the output power rail received from each of the buck controllers.Type: ApplicationFiled: March 30, 2015Publication date: October 8, 2015Inventors: Sanjay Gurlahosur, Rajdeep Mukhopadhyay