Abstract: An example semiconductor package comprises a semiconductor die having a top surface, a passivation layer over the top surface, a first metal layer on the first passivation layer, an antenna formed in the first metal layer and offset from the semiconductor die, the antenna having a slot bow-tie configuration, a transmission line formed in the first metal layer, the transmission line coupling the semiconductor die to the antenna, and an insulating material separating the first metal layer from a second metal layer, the second metal layer configured to function as a ground reflector for the antenna. The second metal layer may extend below the antenna and the semiconductor die.

Abstract: An example semiconductor package comprises a ceramic header having a first open space separated from a second open space by a ceramic barrier. A first heat sink is attached to a bottom of the ceramic header below the first open area. A first integrated circuit (IC) die is mounted on the first heat sink. A second heat sink is attached to a bottom of the ceramic header below the second open area. A second IC die is mounted on the second heat sink. A capacitive interface is disposed in the ceramic barrier between the first IC die and the second IC die. The capacitive has a plurality of capacitive elements alternating with a plurality of shielding elements. The capacitive elements are tunable over a range of capacitive values.

Abstract: A semiconductor device is described herein. The semiconductor device generally includes a metal fabrication layer disposed on a substrate. The semiconductor device generally includes a dielectric layer having a first plurality of vias aligned with a first metallization region of the metal fabrication layer and a second plurality of vias aligned with a second metallization region of the metal fabrication layer, the dielectric layer disposed on top of the metal fabrication layer. The semiconductor device generally includes a metal layer disposed on the dielectric layer and having a plurality of metal routings, each of the metal regions disposed over both the first metallization region and the second metallization region, each of the plurality of metal routings have a same width. The semiconductor device generally includes an insulation layer disposed on the metal layer, the insulation layer having a plurality of openings to the metal routings of the metal layer.

Abstract: An example semiconductor package comprises a ceramic header having a top surface and a cavity formed within the ceramic header. The cavity is open at the top surface. A semiconductor die is mounted within the cavity of the ceramic header. A lid structure is coupled to the top surface of the ceramic header. The lid structure and ceramic header form a portion of a package enclosing the semiconductor die. One or more silver tubes are in contact with a first surface of the semiconductor die and with a first surface of the lid structure. A seal ring is located between the top surface of the ceramic header and the lid structure. The seal ring couples the lid structure to the ceramic header. The one or more silver tubes are hollow and filled with a getter material.

Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to th first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.

Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.

Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.

Abstract: Described examples include a packaged device including a first object and a second object spaced from each other by a gap, each object having a first surface and an opposite second surface, the first surfaces of the first object and the second object including first terminals. A structure includes at least two conductors embedded in a dielectric casing consolidating a configuration and organization of the at least two conductors, the at least two conductors having end portions un-embedded by the dielectric casing. An end portion of at least one of the at least two conductors is electrically connected to a first terminal of the first object, and an opposite end portion of the at least one of the at least two conductors is electrically connected to a respective first terminal of the second object, the at least two conductors electrically connecting the first object and the second object.

Abstract: One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.

Abstract: One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.