Abstract: Methods and systems for securing data are provided. For example, one method includes receiving at an adapter, data with a first type of error protection code from a host memory of a computing device; adding by the adapter a second type of error protection code to the data before removing the first type of error protection code; generating by the adapter, a frame header for the data with a protocol specific protection code and a third type of error protection code, where the third type of error protection code is generated without using any frame header field; encrypting by the adapter, the data, the protocol specific protection code and the third type of error protection code; and transmitting by the adapter, the encrypted data with encrypted protocol specific protection code and encrypted third type of error protection code to a receiving adapter coupled to the adapter by a network link.

Abstract: Methods and systems for a device interfacing with a computing system are provided. The device is configured to send an input/output status block (IOSB) and an interrupt message to the processor of a computing system interfacing upon completion of an operation. The device generates the interrupt message while the IOSB is waiting to be transmitted; and transmits the IOSB to the processor, followed by the interrupt message, using a same data path for both the IOSB and the interrupt message. Furthermore, the device is configured to detect a request from the processor of the computing system interfacing to clear an interrupt status maintained by the device at a hardware location; send a message to the processor to de-assert the interrupt status and in parallel, clear the hardware location to clear the interrupt status such that the computing system can transfer information to the device for a next operation.

Abstract: Methods and systems for routing control blocks is provided. One method includes receiving a control block from a computing device at an adapter having a plurality of hardware engines for processing control blocks, where the control blocks are to read data, write data, obtain status for an input/output request and perform a management task; evaluating the control block by the adapter to determine that the control block is a continuation control block for data transfer using more than one control block; is a direct route control block for a specific hardware engine; or is for a management task; routing the control block to a same hardware engine when the control block is a continuation control block; and routing the control block to a master hardware engine from among the plurality of hardware engines, when the control block is for the management task.

Abstract: Method and system for sending data from a memory of a computing system interfacing with a device is provided. An input/output control block (IOCB) from the computing system for transferring the data from the memory of the computing system is received by the device. The device then allocates a plurality of DMA channels to the IOCB for transferring the data from the memory of the computing system when a number of pending input/output (I/O) requests when the IOCB is received is less than a number of available direct memory access (DMA) channels to receive the data from the memory of the computing system.

Abstract: A system comprising a plurality of virtual machines executed by a computing system; and an adapter; wherein the adapter includes a direct memory access (DMA) module for transferring control blocks to and from a computing system memory to an adapter memory, where the computing system memory has dedicated memory locations for each virtual machine to place the control blocks and the adapter memory has dedicated memory locations for storing the control blocks generated by each of the plurality of virtual machines.

Abstract: A system is provided.

Abstract: An adapter having a plurality of functions and a plurality of ports, in which the mapping between functions and ports is configurable. In certain embodiments, device memory can be programmed with a desired mapping scheme that overrides a default mapping scheme for the adapter. In certain embodiments, device memory can be reprogrammed with a different desired mapping to enable the adapter to dynamically respond to system conditions.

Abstract: A method and a host bus adapter (HBA) are provided. The HBA includes a first port that is enabled for use in a storage area network; and a second port that is enabled after a user acquires a transceiver with a security key, wherein the HBA firmware reads the security key and validates the transceiver and enables a function for the second port. The method includes coupling a transceiver to an inactive port, wherein the transceiver stores a security key; validating the transceiver by reading the security key; enabling a function for the inactive port; downloading a software component for the inactive port; and operating the host bus adapter with more than one functional port.

Abstract: An adapter having a plurality of functions and a plurality of ports, in which the mapping between functions and ports is configurable. In certain embodiments, device memory can be programmed with a desired mapping scheme that overrides a default mapping scheme for the adapter. In certain embodiments, device memory can be reprogrammed with a different desired mapping to enable the adapter to dynamically respond to system conditions.

Abstract: Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system, wherein a size of data transfer is specified in the DMA request and is based on a minimum data transfer size; and submitting the DMA request to an arbitration module to gain access to a bus for transferring the information and while the arbitration module arbitrates between pending DMA requests, the DMA module monitors status from plural buffer slots and before the DMA request is granted, the DMA module modifies the size of data transfer based on available buffer slots.

Abstract: A host bus adapter coupled to a network and a host computing system is provided. The host bus adapter includes a direct memory access (“DMA”)mode detection module that receives a DMA channel identifier information from an arbitration module that receives requests from plural DMA channels, wherein the DMA mode detection module includes a DMA counter that counts a number of times a single DMA channel is exclusively serviced by the arbitration module and if the DMA counter value is equal to a threshold value, then the DMA mode detection module enables a single channel mode during which standard transaction rules are ignored for determining DMA request lengths for transferring data. The single channel mode is enabled for a certain duration. The host bus adapter includes a rule based segmentation logic that may be enabled and/or disabled by host bus adapter firmware and/or detection of a single channel mode condition.

Abstract: Method and system for processing read requests sent by a network interface device to a host system is provided. The method includes sending staggered read requests within a programmable time interval (“T”), wherein a transmit direct memory access (DMA) module sends more than one read request to the host system within the time interval T; placing data received from the host system in response to the read requests in independent slots of a transmit buffer; and unloading the transmit buffer slots based on an unload command, wherein the unload command is based on a mapping of read requests corresponding to transmit buffer slot locations where data from the host system is stored, and data is sent from the transmit buffer to a network device in the same order as the read requests that are sent from the network interface device to host system.

Abstract: Method and system for optimizing DMA request processing is provided. The system includes a HBA that uses a dynamic DMA maximum write burst count sizing to optimize processing of write and read requests, wherein the HBA includes a DMA optimizer module that selects a certain write burst size to adjust performance when read and write DMA requests are being utilized. The DMA optimizer module can toggle between write and read request priority based on a maximum write request burst size. A shorter maximum write burst size provides more opportunity to issue read requests and a larger maximum burst size provides a better write request performance. The method includes, evaluating a read request throughput rate; evaluating a write request throughput rate; evaluating a read request utilization rate; evaluating a write request utilization rate; and adjusting a maximum write burst size.

Abstract: Method and system for forcing PCI-Express errors in a downstream path and upstream path is provided. The downstream path method includes enabling an error forcing function; determining if an additional stimulus is used for enabling an error condition; sending the additional stimulus to trigger error detection; and detecting a forced error condition at a qualifying event. The upstream path method includes enabling an error forcing function; determining if an additional stimulus is used for enabling an error condition; sending a stimulus to trigger error detection; inserting a forced error condition at a qualifying event; wherein a downstream PCI-Express device inserts the error condition; and detecting the forced error condition; wherein an upstream PCI-Express device detects the forced error condition.

Abstract: A method and system for performing data integrity process is provided. The method includes selecting a cyclic redundancy code (“CRC”) mode from amongst append, validate and keep, and validate and remove mode. If the append mode is selected, then CRC is appended after each data block boundary. A CRC seed value is incremented for each data block providing a unique CRC value for each data block. If validate and keep mode is selected, then CRC accompanying any data is compared to CRC that may have been accumulated. If validate and remove mode is selected, then CRC is first validated and then CRC is removed before data is sent out. The system includes CRC logic that allows firmware running on an adapter to select one of plural CRC modes including append, validate and keep, and validate and remove mode.