Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; and a channel region under the gate structure, the channel region having a first portion including a first thickness and a second portion having a second thickness greater than the first thickness, the second portion being positioned remotely from the gate structure.

Abstract: A scan flip-fop is designed to hold the state of the slave latch during scan shifting. This allows an ATPG tool to develop robust delay path tests using combinational scan flip-flop models. Combinational scan flip-flop models suffice because the launch can be done in the cycle before test enable goes active and capture can be performed during the cycle in which test enable is active. Thus, multiple clocks during the capture cycle are not necessary and, therefore, sequential delay path ATPG is not necessary. It is only necessary for the ATPG tool to store the last parallel vector in a buffer. The dynamic latch used for the scan slave latch is made small and slow, thereby increasing the delay along the data path during shifting, making the cell immune to hold time violation for any reasonable amount of clock skew.