Abstract: In certain aspects, an apparatus includes a gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal. The apparatus also includes a toggle circuit having an output, wherein the toggle circuit is configured to toggle a logic state at the output of the toggle circuit based on the enable signal. The apparatus further includes a multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, the second input of the multiplexer is coupled to the output of the toggle circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal, and couple the selected one of the first input and the second input to the output of the multiplexer.

Abstract: Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.

Abstract: Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

Abstract: Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

Abstract: Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

Abstract: A CPU core may be woken up from a power-saving mode in a portable computing device in a manner that depends upon whether the wake-up event source is a snoop request or an interrupt. A core power controller may monitor for and detect snoop requests and interrupts directed to the CPU core while the CPU core is in the power-saving mode. In response to detecting a snoop request, the core power controller may wake up snoop-related components of the CPU core while refraining from waking up non-snoop-related components of the CPU core. In response to detecting an interrupt, the core power controller may wake up both the snoop-related components and the non-snoop-related components of the CPU core.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

Abstract: Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.

Abstract: Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

Abstract: Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.

Abstract: An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The GDHS cells are configured to switch power on and to switch power off to the first set of standard cells. The IC further includes a plurality of CHS cells in the first IC portion. The CHS cells are configured to switch power on and to switch power off to the second set of standard cells in the second IC portion.

Abstract: Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.

Abstract: An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The GDHS cells are configured to switch power on and to switch power off to the first set of standard cells. The IC further includes a plurality of CHS cells in the first IC portion. The CHS cells are configured to switch power on and to switch power off to the second set of standard cells in the second IC portion.

Abstract: Apparatuses and methods to relay a clock signal to clock loads are presented. An apparatus includes a clock spine to conduct a clocking signal. The clock spine includes multiple taps points distributed unevenly on the clock spine. The apparatus further includes multiple clock buffers. Each of the multiple clock buffers is connected to a corresponding one of the multiple tap points. The method includes conducting a clocking signal on a clock spine having multiple taps points. The multiple tap points are distributed unevenly on the clock spine. The method further includes buffering the clocking signal at each of the multiple tap points. Another method includes forming a clock spine to conduct a clocking signal. The clock spine includes multiple taps points. The multiple tap points are distributed unevenly on the clock spine. The method further includes forming multiple clock buffers.