Abstract: In some examples, a receiver can include a sampler circuit that can be configured to process a data input signal corresponding to a current bit received at a receiver based on a capacitive weighted signal to compensate for distortion effects that a previously received bit at the receiver has on the data input signal. The receiver can include a capacitive coupling feedback circuit that can be configured to generate the capacitive weighted signal corresponding to a weighted detected bit of the previously received bit based on a capacitance of a subset of capacitors of a plurality of capacitors of the feedback circuit. The capacitive coupling feedback circuit can be configured to selectively control a number of capacitors of the plurality of capacitors that are connected in parallel corresponding to the subset of capacitors to control an amount of weight applied to the detected bit to generate the capacitive weighted signal.

Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.

Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.

Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.

Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.

Abstract: Apparatuses for generating negative impedance compensation are provided. Embodiments include a differential amplifier having a first output and a second output; a capacitor coupled between the first output and the second output of the differential amplifier; a first negative impedance cross-coupled circuit having a first output and a second output; and a resistance control circuit coupled in series between the first output and the second output of the differential amplifier and the first output and the second output of the first negative impedance cross-coupled circuit.

Abstract: Apparatuses for generating negative impedance compensation are provided. Embodiments include a differential amplifier having a first output and a second output; a capacitor coupled between the first output and the second output of the differential amplifier; a first negative impedance cross-coupled circuit having a first output and a second output; and a resistance control circuit coupled in series between the first output and the second output of the differential amplifier and the first output and the second output of the first negative impedance cross-coupled circuit.

Abstract: Circuits and methods for sampling differential input signals having wide input swings including voltages below ground potential, and capable of operating on a single positive supply voltage are disclosed. In an embodiment, the circuit includes a first input switch circuit and a second input switch circuit, a sample and hold circuitry and an operational amplifier. Each of the first and second input switch circuits includes serially connected PMOS switch and NMOS switch for receiving a differential input signal. The sample and hold circuitry includes a first sampling capacitor, a second sampling capacitor and a plurality of switches. The switches are configured to provide the differential input signal to the sampling capacitors for the sampling in a sample phase, and are configured to provide the sampled differential input signal at an output of the operational amplifier in a hold phase.

Abstract: Circuits and methods for sampling differential input signals having wide input swings including voltages below ground potential, and capable of operating on a single positive supply voltage are disclosed. In an embodiment, the circuit includes a first input switch circuit and a second input switch circuit, a sample and hold circuitry and an operational amplifier. Each of the first and second input switch circuits includes serially connected PMOS switch and NMOS switch for receiving a differential input signal. The sample and hold circuitry includes a first sampling capacitor, a second sampling capacitor and a plurality of switches. The switches are configured to provide the differential input signal to the sampling capacitors for the sampling in a sample phase, and are configured to provide the sampled differential input signal at an output of the operational amplifier in a hold phase.