Patents by Inventor Rajesh KAPALURU

Rajesh KAPALURU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for providing an area efficient and design rule check (DRC) friendly power sequencer for digital circuits
    Patent number: 10003325
    Abstract: According to one general aspect, an apparatus may include a power header and a logic circuit. The power header may include a gate terminal, a first channel terminal, a second channel terminal, and a bulk terminal coupled with a first voltage power signal. The power header may be configured to perform one of dynamically coupling or decoupling a logic circuit with the first voltage power signal. The logic circuit may include a bulk terminal coupled with a second voltage power signal and a power terminal that is either dynamically coupled or decoupled, as determined by the power header, with the first voltage power signal. A power sequencing signal may be included in the apparatus and may be configured to control the power header such that, when active, the power header couples the logic circuit with the first voltage power signal after the second voltage power signal is high.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 19, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sumeer Goel, Kenneth Hicks, Jan-Michael Huber, Rajesh Kapaluru, Prashant Kenkare
  • SYSTEM AND METHOD FOR PROVIDING AN AREA EFFICIENT AND DESIGN RULE CHECK (DRC) FRIENDLY POWER SEQUENCER FOR DIGITAL CIRCUITS
    Publication number: 20180034448
    Abstract: According to one general aspect, an apparatus may include a power header and a logic circuit. The power header may include a gate terminal, a first channel terminal, a second channel terminal, and a bulk terminal coupled with a first voltage power signal. The power header may be configured to perform one of dynamically coupling or decoupling a logic circuit with the first voltage power signal. The logic circuit may include a bulk terminal coupled with a second voltage power signal and a power terminal that is either dynamically coupled or decoupled, as determined by the power header, with the first voltage power signal. A power sequencing signal may be included in the apparatus and may be configured to control the power header such that, when active, the power header couples the logic circuit with the first voltage power signal after the second voltage power signal is high.
    Type: Application
    Filed: September 29, 2016
    Publication date: February 1, 2018
    Inventors: Sumeer GOEL, Kenneth HICKS, Jan-Michael HUBER, Rajesh KAPALURU, Prashant KENKARE